Wafer level packaging of infrared camera detectors

Patent metadata

Field	Value
Publication number	US-9513172-B2
Application number	US-201313750709-A
Country	US
Kind code	B2
Filing date	Jan 25, 2013
Priority date	Jul 27, 2010
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An infrared detector useful in, e.g., infrared cameras, includes a substrate having an array of infrared detectors and a readout integrated circuit interconnected with the array disposed on an upper surface thereof, for one or more embodiments. A generally planar window is spaced above the array, the window being substantially transparent to infrared light. A mesa is bonded to the window. The mesa has closed marginal side walls disposed between an outer periphery of a lower surface of the window and an outer periphery of the upper surface of the substrate and defines a closed cavity between the window and the array that encloses the array. A solder seal bonds the mesa to the substrate so as to seal the cavity.

First claim

What is claimed is:

1. An infrared detector, comprising:
a substrate having an array of infrared detectors and a readout integrated circuit interconnected with the array disposed on an upper surface thereof;
a generally planar window spaced above the array, the window being substantially transparent to infrared light;
a mesa bonded to the window and to the substrate, the mesa having closed marginal side walls disposed between an outer periphery of a lower surface of the window and an outer periphery of the upper surface of the substrate and defining a closed cavity between the window and the substrate that encloses the array, and wherein an upper surface of the side walls of the mesa are bonded to the lower surface of the window by a layer of oxide of the semiconductor, and a lower surface of the side walls of the mesa are bonded to the substrate; and,
a solder seal bonding the mesa to the substrate so as to seal the cavity.

2. The infrared detector of claim 1 , wherein the mesa and the window comprise a semiconductor.

3. The infrared detector of claim 2 , wherein the lower surface of the side walls of the mesa are bonded to the upper surface of the substrate by a ring of solder to form the solder seal, and wherein the array of infrared detectors comprise an array of microbolometers.

4. The infrared detector of claim 3 , wherein at least one of the mesa, the substrate and the window comprises silicon.

5. The infrared detector of claim 3 , further comprising at least one solder capture ring disposed on the substrate adjacent to the ring of solder.

6. The infrared detector of claim 1 , further comprising at least one getter disposed on a lower surface of the window.

7. The infrared detector of claim 1 , further comprising at least one anti-reflective coating disposed on an upper and/or a lower surface of the window.

8. The infrared detector of claim 1 , further comprising at least one electrical test pad disposed on the upper surface of the substrate adjacent to the outer periphery of the window and coupled to the readout integrated circuit.

9. The infrared detector of claim 1 , wherein the mesa and the window comprise a semiconductor, wherein an upper surface of the side walls of the mesa are bonded to the lower surface of the window by a layer of oxide of the semiconductor, and wherein the cavity and a lower surface of the window is formed using a Deep Reactive Ion Etching (DRIE) process followed by a hydrofluoric acid etch to remove the oxide across a portion of the window.

10. The infrared detector of claim 1 , wherein the detector comprises one of a plurality of infrared detectors singulated from a bonded sandwich of a window wafer and a bolometer wafer, and wherein the infrared detector is part of an infrared camera.

11. A method for making an infrared detector, the method comprising:
providing a window wafer having a layer of oxide sandwiched between two layers of a semiconductor;
forming an array of cavities in a surface of the window wafer, each cavity defining a window substantially transparent to infrared light and surrounded by a mesa having closed marginal side walls, wherein upper surfaces of the side walls of the mesa are bonded to a lower surface of the window wafer by a layer of oxide of the semiconductor, adjacent rows and columns of the array being separated from each other by dicing lanes;
providing a detector wafer having an upper surface with an array of infrared detector arrays corresponding in size and location to be disposed within the array of cavities in the window wafer, and a corresponding array of readout integrated circuits respectively interconnected with associated ones of the infrared detector arrays disposed thereon, adjacent rows and columns of the infrared detector array being separated from each other by dicing lanes;
aligning the window wafer over the detector wafer such that the cavities of the window wafer are respectively disposed over corresponding ones of the infrared detector arrays; and,
bonding lower surfaces of the side walls of the mesas with the upper surface of the detector wafer such that each of the cavities is sealed and a plurality of infrared detectors is defined between the two wafers.

12. The method of claim 11 , wherein the forming of the array of cavities comprises:
etching the surface of the window wafer down to the oxide layer to form the array of cavities and associated mesas, and;
removing the oxide layer from the surface of the window wafer in such a way that lower surfaces of the windows remain substantially smooth and planar while the respective marginal side walls of each of the mesas remain bonded to the window wafer by the layer of oxide.

13. The method of claim 12 , wherein the etching of each of the mesas comprises using a Deep Reactive Ion Etching (DRIE) process, and wherein the removing the oxide layer comprises a hydrofluoric acid etch process.

14. The method of claim 11 , wherein the bonding comprises:
forming a solder ring on a lower surface of each of the mesas;
forming an array of solder rings on the upper surface of the detector wafer respectively corresponding in size and location to the solder rings on the mesas on the window wafer;
evacuating at least partially each of the cavities; and,
fusing the solder rings on the mesas with corresponding ones of the solder rings on the upper surface of the detector wafer.

15. The method of claim 14 , wherein the array of solder rings are formed on the upper surface of the detector wafer utilizing photolithography techniques.

16. The method of claim 14 , further comprising forming at least one solder capture ring on the detector wafer adjacent to each of the solder rings thereon.

17. The method of claim 11 , further comprising forming an anti-reflective coating on at least one of an upper and a lower surface of each of the windows.

18. The method of claim 11 , further comprising:
forming a getter on a lower surface of each of the windows; and,
firing the getters during the bonding of the wafers.

19. The method of claim 11 , further comprising:
slicing through the dicing lanes of the window wafer to expose test pads on the upper surface of the detector wafer; and,
performing a wafer level test of at least some of the plurality of infrared detectors using the exposed test pads.

20. The method of claim 11 , further comprising slicing through the dicing lanes of the detector wafer to singulate the plurality of infrared detectors therefrom.

Assignees

• Flir Systems

Inventors

• Carlson Gregory A
• Matson Alex
• Sharpe Andrew
• Beard Davey
• Schweikert Paul
• Simes Robert

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H04N23/52

  Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements · CPC title

• G01J5/046 Primary

  Materials; Selection of thermal materials · CPC title

• H04N23/23

  from thermal infrared radiation · CPC title