Fault containment routing

Patent metadata

Field	Value
Publication number	US-9510439-B2
Application number	US-201414297825-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Mar 13, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.

First claim

What is claimed is:

1. A circuit board comprising:
a first fault containment region defined, at least in part, by first and second metal layers coupled to ground; the first fault containment region including:
a first signal layer between the first and second metal layers;
a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer; and
a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer; and

a second fault containment region in a plurality of layers below the first fault containment region, the second fault containment region defined, at least in part, by a fifth metal layer and the second metal layer, the second fault containment region including:
a second signal layer between the second and fifth metal layers;
a sixth metal layer between the second and fifth metal layers, the sixth metal layer connected to the second signal layer to provide a return path for the second signal layer; and
a seventh metal layer between the second and fifth metal layers, the seventh metal layer connected to the second signal layer to provide power for the second signal layer.

2. The circuit board of claim 1 , wherein the first, second, and fifth metal layers are not connected to the first signal layer, the fourth metal layer, the second signal layer, or the seventh metal layer.

3. The circuit board of claim 1 , wherein the first, second, and fifth metal layers are either not connected to one or both of the third metal layer and the fifth metal layer, or only connected to one or both of the third metal layer and the fifth metal layer near an edge of the circuit board.

4. The circuit board of claim 1 , wherein the first, second, and fifth metal layers are each composed of a continuous metal sheet.

5. The circuit board of claim 1 , wherein the third and fourth metal layers are connected to the first signal layer such that electric current used by components in the first signal layer propagates through the third and fourth metal layers,
wherein the seventh and eighth metal layers are connected to the second signal layer such that electric current used by components in the second signal layer propagates through the seventh and eighth metal layers.

6. The circuit board of claim 1 , comprising:
a dielectric material between each layer.

7. The circuit board of claim 1 , comprising:
a through board signal via connected to a signal trace in the second signal layer, the through board signal via extending from the second signal layer through the second metal layer, the first signal layer, the fourth metal layer, the third metal layer, and the first metal layer;
an electrically conductive ring surrounding the signal via in the first signal layer; and
a dielectric material between the electrically conductive ring and the through board signal via; and
a through board ground via connecting the electrically conductive ring to the first metal layer.

8. The circuit board of claim 1 , comprising:
one or more surface mount connectors on a first surface of the circuit board;
an electrically conductive ring surrounding the one or more surface mount connectors; and
a dielectric material between the electrically conductive ring and the one or more surface connectors; and
a through board ground via connecting the electrically conductive ring to the first metal layer.

9. The circuit board of claim 1 , comprising:
a trace extending across a first surface of the circuit board;
a through board ground via connecting an electrically conductive ring to the first metal layer, wherein the trace demarcates a third lateral fault containment region on the first surface from a fourth lateral fault containment region on the first surface.

10. The circuit board of claim 1 , comprising:
a first trace extending across the circuit board in the first signal layer;
a second trace aligned with the first trace and extending across the circuit board in the third metal layer;
a third trace aligned with the first trace and extending across the circuit board in the fourth metal layer; and
one or more through board ground vias coupling the first trace, second trace, and third trace to one or both of the first metal layer and the second metal layer.

11. A redundant system including a fault containment circuit board, the system comprising:
a first redundant component and a second redundant component, wherein the first redundant component and the second redundant component are configured to perform the same task;
a circuit board including:
a first fault containment region defined, at least in part, by first and second metal layers connected to ground; the first fault containment region including:
a first signal layer between the first and second metal layers;
a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer; and
a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power for the first signal layer; and

a second fault containment region in a plurality of layers below the first fault containment region, the second fault containment region defined, at least in part, by a fifth metal layer and the second metal layer, the second fault containment region including:
a second signal layer between the second and fifth metal layers;
a sixth metal layer between the second and fifth metal layers, the sixth metal layer connected to the second signal layer to provide a return path for the second signal layer; and
a seventh metal layer between the second and fifth metal layers, the seventh metal layer connected to the second signal layer to provide power to the second signal layer;

wherein the first redundant component is coupled to the first signal layer and not the second signal layer,
wherein the second redundant component is coupled to the second signal layer and not the first signal layer.

12. The redundant system of claim 11 , wherein the first, second, and fifth metal layers are not connected to the first signal layer, the fourth metal layer, the second signal layer, or the seventh metal layer.

13. The redundant system of claim 11 , wherein the first, second, and fifth metal layers are either not connected to one or both of the third metal layer and the fifth metal layer, or only connected to one or both of the third metal layer and the fifth metal layer near an edge of the circuit board.

14. The redundant system of claim 11 , wherein the first, second, and fifth metal layers are each composed of a continuous metal sheet.

15. The redundant system of claim 11 , wherein the third and fourth metal layers are connected to the first signal layer such that electric current used by components in the first signal layer propagates through the third and fourth metal layers,
wherein the seventh and eighth metal layers are connected to the second signal layer such that electric current used by components in the second signal layer propagates through the seventh and eighth metal layers.

16. The redundant system of claim 11 , comprising:
a dielectric material between each layer.

17. A circuit board comprising:
a through board signal via connected to a signal trace in a first signal layer, the through board signal via extending from the first signal layer through a second signal layer;
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Assignees

• Honeywell Int Inc

Inventors

• Martin Kenneth Lee
• De La Torre Lucilo
• Peterson James Frederick
• Cole Jonathan

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H05K2201/09309

  Core having two or more power planes; Capacitive laminate of two power planes · CPC title

• H05K2201/09536

  Buried plated through-holes, i.e. plated through-holes formed in a core before lamination · CPC title