Method and apparatus for reordered binarization of syntax elements in CABAC

Patent metadata

Field	Value
Publication number	US-9509989-B2
Application number	US-201214234151-A
Country	US
Kind code	B2
Filing date	Aug 2, 2012
Priority date	Aug 4, 2011
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method and apparatus of context-based adaptive binary arithmetic encoding/decoding for syntax elements of one or more blocks are disclosed. According to one embodiment of the present invention, the binarization results of the x and y positions of the last significant coefficient of a transform unit are reordered by collecting the bypass bins together. According to another embodiment of the present invention, binarization results of syntax elements from two or more of four Intra N×N prediction units, including prev_intra_luma_pred_flag, rem_intra_luma_pred_mode, and mpm_idx are reordered by collecting the bypass bins together. In yet another embodiment according to the present invention, the binarization results of other syntax elements are also reordered by collecting bypass bins together. Furthermore, the above reordering of binarization results may be used for binarization results corresponding to a block and its neighboring blocks.

First claim

The invention claimed is:

1. A method of context-based adaptive binary arithmetic decoding for syntax elements of a coding unit, wherein the coding unit is partitioned into four PUs (prediction units) in an N×N intra prediction mode, the method comprising:
receiving in a circuit reordered bins comprising a first part and a second part, wherein the first part comprises regular bins associated with each of two or more PUs and the second part comprises first bypass bins or second bypass bins associated with said each of two or more PUs, wherein the first bypass bins are reordered by collecting bypass bins related to an index for a most probable mode associated with said two or more PUs together and the second bypass bins are reordered by collecting bypass bins related to a remaining prediction mode associated with said two or more PUs together;
determining in a circuit a first codeword corresponding to a first syntax element for said each of two or more PUs, wherein the first codeword comprises the regular bins, and wherein the first syntax element corresponds to an indication of intra prediction mode selection for said each of two or more PUs;
determining in a circuit a second codeword corresponding to a second syntax element for said each of two or more PUs if the indication corresponds to most-probable-mode coding, wherein the second syntax element corresponds to the index for a most probable mode, and wherein the second codeword comprises the first bypass bins;
determining in a circuit a third codeword corresponding to a third syntax element for said each of two or more PUs if the indication corresponds to remaining-prediction-mode coding, wherein the third syntax element corresponds to the remaining prediction mode, wherein the third codeword comprises the second bypass bins; and
providing by a circuit the first syntax element, the second syntax element and the third syntax element for said each of two or more PUs.

2. The method of claim 1 , wherein the first part comprises the regular bins associated with said four PUs, and wherein the second part comprises the first bypass bins or the second bypass bins associated with each of said four PUs.

3. A method of context-based adaptive binary arithmetic coding for syntax elements of a coding unit, wherein the coding unit is partitioned into four PUs (prediction units) in an N×N intra prediction mode, the method comprising:
receiving in a circuit a first syntax element for each PU, wherein the first syntax element corresponds to an indication of intra prediction mode selection for said each PU;
receiving in a circuit a second syntax element for said each PU if the indication corresponds to most-probable-mode coding, wherein the second syntax element corresponds to an index for a most probable mode;
receiving in a circuit a third syntax element for said each PU if the indication corresponds to remaining-prediction-mode coding, wherein the third syntax element corresponds to a remaining prediction mode;
determining in a circuit a first codeword for the first syntax element for said each PU, wherein the first codeword comprises regular bins;
determining in a circuit a second codeword for the second syntax element for said each PU if the indication corresponds to the most-probable-mode coding, wherein the second codeword comprises reordered first bypass bins;
determining in a circuit a third codeword for the third syntax element for said each PU if the indication corresponds to the remaining-prediction-mode coding, wherein the third codeword comprises reordered second bypass bins;
determining in a circuit a first part, wherein the first part comprises the regular bins associated with two or more PUs;
determining in a circuit a second part, wherein the second part comprises the first bypass bins or the second bypass bins associated with each of said two or more PUs, wherein the first bypass bins are reordered by collecting bypass bins related to the index for a most probable mode associated with said two or more PUs together and the second bypass bins are reordered by collecting bypass bins related to the remaining prediction mode associated with said two or more PUs together; and
providing by a circuit the first part and the second part for binary arithmetic coding, wherein the first part is processed by regular coding and the second part is processed by bypass coding.

4. The method of claim 3 , wherein the first part comprises the regular bins associated with said four PUs, and wherein the second part comprises the first bypass bins or the second bypass bins associated with each of said four PUs.

5. A device for context-based adaptive binary arithmetic decoding for syntax elements of a coding unit, wherein the coding unit is partitioned into four PUs (prediction units) in an N×N intra prediction mode, the device comprising:
a first interface circuit configured to receive reordered bins comprising a first part and a second part, wherein the first part comprises regular bins associated with each of two or more PUs and the second part comprises first bypass bins or second bypass bins associated with said each of two or more PUs, wherein the first bypass bins are reordered by collecting bypass bins related to an index for a most probable mode associated with said two or more PUs together and the second bypass bins are reordered by collecting bypass bins related to a remaining prediction mode associated with said two or more PUs together;
a first circuit configured to determine a first codeword corresponding to a first syntax element for said each of two or more PUs, wherein the first codeword comprises the regular bins, and wherein the first syntax element corresponds to an indication of intra prediction mode selection for said each of two or more PUs;
a second circuit configured to determine a second codeword corresponding to a second syntax element for said each of two or more PUs if the indication corresponds to most-probable-mode coding, wherein the second syntax element corresponds to the index for a most probable mode, and wherein the second codeword comprises the first bypass bins;
a third circuit configured to determine a third codeword corresponding to a third syntax element for said each of two or more PUs if the indication corresponds to remaining-prediction-mode coding, wherein the third syntax element corresponds to the remaining prediction mode, wherein the third codeword comprises the second bypass bins; and
a second interface circuit configured to provide the first syntax element, the second syntax element and the third syntax element for said each of two or more PUs.

6. The device of claim 5 , wherein two or more of the first circuit, the second circuit, the third circuit, the first interface circuit, and the second interface circuit are implemented by an integrated circuit.

7. A device for context-based adaptive binary arithmetic coding for syntax elements of a coding unit, wherein the coding unit is partitioned into four PUs (prediction units) in an N×N intra prediction mode, the device comprising:
a first interface circuit configured to receive a first syntax element for each PU, wherein the first syntax element corresponds to an indication of intra prediction mode selection for said each PU;
a second interface circuit configured to receive a second syntax element for said each PU if the indication corresponds to most-probable-mode coding, wherein the second syntax element corresponds to an index for a most probable mode;
a third interface circuit configured to receive a third syntax element for said each PU if the indication corresponds to remaining-prediction-mode coding, wherein the third syntax element corresponds to a remaining prediction mode;
a first circuit configured to determine a first codeword fo

Assignees

• Chuang Tzu-Der
• Chen Ching-Yeh
• Huang Yu-Wen
• Hfi Innovation Inc

Inventors

• Chuang Tzu-Der
• Chen Ching-Yeh
• Huang Yu-Wen

Classifications

• H04N19/70 Primary

  characterised by syntax aspects related to video coding, e.g. related to compression standards · CPC title

• H04N19/91

  Entropy coding, e.g. variable length coding [VLC] or arithmetic coding · CPC title

• H04N19/436

  using parallelised computational arrangements · CPC title

• H04N19/88

  involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks · CPC title

• H04N19/159

  Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction · CPC title