Electronic circuit and method for operating a transistor arrangement

Patent metadata

Field	Value
Publication number	US-9509284-B2
Application number	US-201414196250-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.

First claim

What is claimed is:

1. An electronic circuit, comprising:
a transistor arrangement with a first type transistor device and at least one second type transistor device, each comprising a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel; and
a drive circuit coupled to the control node of the first type transistor device and the control node of the second type transistor device, and configured to receive an input signal,
wherein each of the first type transistor device and the second type transistor device comprises a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG, wherein the field plate of the first type transistor device is connected to one of the control node and the second load node of the first type transistor device,
wherein the drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate the at least one second type transistor device based on the load signal,
wherein the first type transistor device and the at least one second type transistor device are integrated in a common semiconductor body,
wherein the 2DEG of the first type transistor device is insulated from the 2DEG of the at least one second type transistor device by an insulation region,
wherein the insulation region includes a damaged crystal region.

2. An electronic circuit, comprising:
a transistor arrangement with a first type transistor device and at least one second type transistor device, each comprising a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel; and
a drive circuit coupled to the control node of the first type transistor device and the control node of the second type transistor device, and configured to receive an input signal,
wherein each of the first type transistor device and the second type transistor device comprises a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG, wherein the field plate of the first type transistor device is connected to one of the control node and the second load node of the first type transistor device,
wherein the drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate the at least one second type transistor device based on the load signal,
wherein the first type transistor device and the at least one second type transistor device are integrated in a common semiconductor body,
wherein the 2DEG of the first type transistor device is insulated from the 2DEG of the at least one second type transistor device by an insulation region,
wherein the insulation region includes a trench extending through the 2DEG.

3. An electronic circuit, comprising:
a transistor arrangement with a first type transistor device and at least one second type transistor device, each comprising a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel, and
a drive circuit coupled to the control node of the first type transistor device and the control node of the second type transistor device, and configured to receive an input signal,
wherein each of the first type transistor device and the second type transistor device comprises a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG, wherein the field plate of the first type transistor device is connected to one of the control node and the second load node of the first type transistor device,
wherein the drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate the at least one second type transistor device based on the load signal,
wherein the drive circuit is configured to deactivate the at least one second type transistor device by driving the field plate of the at least one second type transistor device to be floating, and by driving the control node of the at least one second type transistor device such that the at least one second type transistor device is in an off-state.

4. The electronic circuit of claim 3 , wherein the drive circuit is configured to activate the at least one second type transistor device by connecting the field plate of the at least one second type transistor device to one of the second load node and the control node of the at least one second type transistor device, and by driving the control node of the at least one second type transistor device dependent on the input signal.

5. The electronic circuit of claim 3 , wherein the drive circuit is configured to drive the control node of the first type transistor device dependent on the input signal.

6. The electronic circuit of claim 3 , wherein the at least one load parameter is selected from the group consisting of:
a current level of a load current through the transistor arrangement;
a temperature of the transistor arrangement; and
a switching frequency of the input signal.

7. The electronic circuit of claim 6 , wherein the drive circuit is configured to activate the at least one second type transistor device when a current level of the load current is above a predefined current threshold, and deactivate the at least one second type transistor device when the current level of the load current is at or below the predefined current threshold.

8. The electronic circuit of claim 6 , wherein the drive circuit is configured to activate the at least one second type transistor device when a temperature level of the temperature is above a predefined temperature threshold, and deactivate the at least one second type transistor device when the temperature level of the temperature is below the predefined temperature threshold.

9. The electronic circuit of claim 6 , wherein the drive circuit is configured to activate the at least one second type transistor device when the switching frequency is below a predefined frequency threshold, and deactivate the at least one second type transistor device when the switching frequency is above the predefined frequency threshold.

10. The electronic circuit of claim 6 , wherein the load signal represents two or more different load parameters.

11. A method, comprising:
obtaining a load signal that represents at least one load parameter of a transistor arrangement that comprises a first type transistor device and at least one second type transistor device;
receiving an input signal by a drive circuit; and
one of activating and deactivating by the drive circuit the at least one second type transistor device based on the load signal,
wherein each of the first type transistor device and the at least one second type transistor device comprises a control node, a load path between a first load node and a second load node, a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG,
wherein the load paths of the first type transistor device and the at least one second type transistor device are connected in parallel,
wherein the field plate of the first type transistor device is connected to one of the control node and the second load node of the first type transistor device,
wherein the first type transistor device and the at least one second type transistor device are integrated in a common semiconductor body,
wherein the 2DEG of the first type transistor device is insulated from the 2DEG of the at least one second typ

Assignees

• Infineon Technologies Austria Ag

Inventors

• Haeberlen Oliver
• Rieger Walter

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/111

  Field plates · CPC title

• H10D84/82

  of only field-effect components · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title