Dual mode power supply controller with charge balance multipliers and charge balance multiplier circuits

Patent metadata

Field	Value
Publication number	US-9509215-B2
Application number	US-201313734327-A
Country	US
Kind code	B2
Filing date	Jan 4, 2013
Priority date	Oct 31, 2012
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A circuit for generating an output current includes a control signal generating circuit that is configured to generate a control signal. The control signal is a function of a level of an analog input voltage signal, and a level of the output current is a function of a level of an analog input current signal and the level of the analog input voltage signal.

First claim

What is claimed is:

1. A circuit for generating an output current, comprising:
a control signal generating circuit that is configured to generate a control signal, wherein the control signal is a function of a level of an analog input voltage signal and wherein an average level of the output current is a function of a level of a varying analog input current signal and the level of the analog input voltage signal; and
a switched current source that is controlled by the control signal and configured to generate the output current with a duty cycle corresponding to the control signal and having a peak level equal to the level of the varying analog input current signal, wherein the duty cycle of the control signal is proportional to the level of the analog input voltage signal.

2. The circuit of claim 1 , further comprising:
a balance capacitor coupled to the switched current source;
wherein a level of the output current is proportional to a product of the level of the varying analog input current signal and the level of the analog input voltage signal.

3. The circuit of claim 2 , further comprising:
an output current mirror coupled to the balance capacitor;
wherein the switched current source receives the varying analog input current signal as an input; and
wherein the balance capacitor is charged by the switched current with the duty cycle corresponding to the control signal and formed from the varying analog input current signal output by the switched current source and is discharged through the output current mirror.

4. The circuit of claim 3 , further comprising a resistor between the balance capacitor and the output current mirror.

5. The circuit of claim 2 , wherein the control signal generating circuit comprises:
a comparator configured to receive the analog input voltage signal and a ramp voltage and to generate the control signal in response to the analog input voltage signal and the ramp voltage; and
a ramp voltage generating circuit coupled to the comparator and configured to generate the ramp voltage.

6. The circuit of claim 5 , wherein the ramp voltage generating circuit comprises:
a current source configured to generate a ramping current;
a ramping capacitor coupled to the current source and configured to be charged by the ramping current;
a transistor switch configured to discharge a ramping voltage from the ramping capacitor in response to a discharge signal; and
a hysteretic comparator configured to compare the ramping voltage with a reference voltage and to generate the discharge signal in response to a comparison of the ramping voltage with the reference voltage.

7. The circuit of claim 5 , wherein the switched current source comprises:
a first transistor having a gate terminal and a drain terminal;
a second transistor having a gate terminal coupled to the gate terminal of the first transistor and a drain terminal, coupled to the drain terminal of the first transistor; and
a switch transistor coupled between the drain terminals of the first and second transistors and the gate terminals of the first and second transistors, wherein the switch transistor has a gate terminal coupled to an output of the comparator and is configured to receive the control signal.

8. The circuit of claim 2 , farther comprising an input current conditioning circuit comprising a first current mirror and a second current mirror coupled to the first current mirror, wherein the first current mirror is configured to supply an input current signal as the varying analog input current signal when the varying analog input current signal is above a threshold level, and wherein the second current mirror is configured to supply a reference current signal as the varying analog input current signal when the varying analog input current signal is below the threshold level.

9. The circuit of claim 2 , wherein the circuit for generating the output current is configured to be switched between a first mode in which the input current signal is nonzero and a second mode in which the varying analog input current signal is zero.

10. The circuit of claim 2 , further comprising a clamping diode coupled to the balance capacitor.

11. The circuit of claim 2 , wherein the output current is given as:
I PK =( V COMP *I CH )/ V LIMIT
where I PK is the output current V COMP is the analog input voltage signal, I CH is the switched current with the duty cycle corresponding to the control signal and formed from the varying analog input current signal, and V LIMIT is a reference voltage.

12. The circuit of claim 11 , wherein a charge that is stored in the balance capacitor is given as (I CH −I PK )DTs, where D is the duty cycle of the control signal and Ts is a period of the control signal, and wherein a charge that is discharged from the balance capacitor is given as I PK (1−D)Ts.

13. The circuit of claim 2 , wherein the switched current source receives a reference current as an input, and wherein the balance capacitor is charged by the varying analog input current signal and is discharged by the switched current source.

14. The circuit of claim 13 , further comprising:
a hysteretic inverter having an input coupled to the balance capacitor; and
a switch coupled to an output of the hysteretic inverter and configured to control the switched current source.

15. The circuit of claim 14 , further comprising:
an output inverter having an input coupled to the output of the hysteretic inverter and configured to generate an output signal having an amplitude that is proportional to the analog input voltage signal.

16. The circuit of claim 15 , further comprising:
a filter configured to filter the output signal of the output inverter; and
an amplifier configured to amplify the filtered output signal of the output inverter.

17. The circuit of claim 13 , wherein the output current signal is given by:
I PK =I CH *V COMP *K
wherein I PK is the output current, I CH is the switched current with the duty cycle corresponding to the control signal and formed from the varying analog input current signal, V COMP is the analog input voltage signal, and K is a constant.

18. The circuit of claim 17 , wherein a charge that is stored in the balance capacitor is given as I CH (1−D)Ts, where D is a duty cycle of the control signal and Ts is a period of the control signal, and wherein a charge that is discharged from the balance capacitor is given as (I FS −I CH )DTs, wherein I FS is the reference current.

19. A circuit for generating an output current, comprising:
a control signal generating circuit that generates a control signal in response to an analog input voltage;
a switched current source that generates the output current in response to the control signal and a variable analog input current signal; and
a balance capacitor coupled to an output of the switched current source;
wherein a duty cycle of the control signal is proportional to a level of the analog input voltage signal; and
wherein a level of the output current is proportional to a product of the variable analog input current signal and the analog input voltage;
an output current mirror coupled to the balance capacitor;
wherein the balance capacitor is charged by a current output by the switched current source and is discharged through the output current mirror.

20. The circuit of claim 19 , wherein the control signal generating circuit comprises:
a comparator configured to receive the analog input voltage and a ramp voltage and to g

Assignees

• Cree Inc

Inventors

• Walters Michael
• Hu Qingcong

Classifications

• H05B45/14

  using electrical feedback from LEDs or from LED modules · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M2001/0009

  Electricity · mapped topic

• H05B33/0848

  Electricity · mapped topic