Voltage regulator with adaptive control

Patent metadata

Field	Value
Publication number	US-9509214-B2
Application number	US-201213997712-A
Country	US
Kind code	B2
Filing date	May 1, 2012
Priority date	May 1, 2012
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Generally, this disclosure describes an apparatus, systems and methods for adaptively controlling a voltage regulator. The apparatus may include a differencing circuit configured to generate an error signal based on a difference between a reference voltage and the output voltage of the voltage regulator; a proportional control circuit coupled to the differencing circuit, the proportional control circuit configured to generate a control signal proportional to the error signal; a derivative control circuit coupled to the differencing circuit, the derivative control circuit configured to generate a control signal based on the derivative of the error signal; a summer circuit coupled to the proportional control circuit and the derivative control circuit, the summer circuit configured to sum the proportional control signal and the derivative control signal; a PWM signal generator circuit coupled to the summer circuit, the PWM generator circuit configured to adjust the PWM modulation based on the summed control signal; and a state monitor circuit configured to monitor the state of the output voltage and perform a gain adjustment on the proportional control signal and the derivative control signal based on the monitored state.

First claim

What is claimed is:

1. A voltage regulator comprising:
a differencing circuit to generate an error signal based on a difference between a reference voltage and an output voltage of said voltage regulator;
a proportional control circuit coupled to said differencing circuit, said proportional control circuit to generate a control signal proportional to said error signal;
a derivative control circuit coupled to said differencing circuit, said derivative control circuit to generate a control signal based on a derivative of said error signal;
a summer circuit coupled to said proportional control circuit and said derivative control circuit, said summer circuit to sum said proportional control signal and said derivative control signal;
a pulse width modulated (PWM) signal generator circuit coupled to said summer circuit, said PWM generator circuit to adjust said PWM modulation based on said summed control signal; and
a state monitor circuit to determine when said output voltage enters a steady state and to adjust a gain of said proportional control signal and said derivative control signal based on said determination, wherein said gain of said derivative control signal is decreased a predetermined programmable period of time after said state monitor circuit determines said output voltage entered said steady state.

2. The voltage regulator of claim 1 , further comprising an integral control circuit coupled to said differencing circuit, said integral control circuit generates a control signal based on an integral of said error signal, and wherein said summer circuit sums said integral control signal to said proportional control signal and said derivative control signal.

3. The voltage regulator of claim 1 , wherein said state monitor circuit increases said gain adjustment on said derivative control signal in response to determining that said output voltage enters a transition state.

4. The voltage regulator of claim 1 , wherein said state monitor circuit decreases said gain adjustment on said proportional control signal in response to determining that said output voltage enters a transition state.

5. The voltage regulator of claim 1 , wherein said state monitor circuit increases said gain adjustment on said proportional control signal in response to detecting that said output voltage enters said steady state.

6. The voltage regulator of claim 1 , wherein a minimum value of said gain adjustment and a maximum value of said gain adjustment are programmable.

7. The voltage regulator of claim 6 , wherein a transition time between said minimum value of said gain adjustment and said maximum value of said gain adjustment is programmable.

8. The voltage regulator of claim 1 , wherein said voltage regulator is selected from the group consisting of a Buck regulator, a Boost regulator and a Buck-Boost regulator.

9. A method for adaptively controlling a voltage regulator, said method comprising:
computing an error signal based on a difference between a reference voltage and an output voltage of said voltage regulator;
generating a control signal proportional to said error signal;
generating a control signal based on a derivative of said error signal;
summing said proportional control signal and said derivative control signal;
adjusting a PWM modulation of said voltage regulator based on said summed control signal;
determining a state of said output voltage of said voltage regulator; and
adjusting a gain of said proportional control signal and said derivative control signal based on said determined state, wherein said gain of said derivative control signal is decreased a predetermined programmable period of time after said state monitor circuit determines said output voltage entered a steady state.

10. The method of claim 9 , further comprising generating a control signal based on an integral of said error signal and summing said integral control signal to said proportional control signal and said derivative control signal.

11. The method of claim 9 , further comprising increasing said gain adjustment on said derivative control signal in response to determining that said output voltage enters a transition state.

12. The method of claim 9 , further comprising decreasing said gain adjustment on said proportional control signal in response to determining that said output voltage enters a transition state.

13. The method of claim 9 , further comprising increasing said gain adjustment on said proportional control signal in response to determining that said output voltage enters said steady state.

14. The method of claim 9 , further comprising programming a minimum value of said gain adjustment and a maximum value of said gain adjustment.

15. The method of claim 14 , further comprising programming a transition time between said minimum value of said gain adjustment and said maximum value of said gain adjustment.

16. One or more non-transitory computer-readable memories which store, singularly or in combination, instructions which when executed by at least one processor result in the following operations for estimating receiver noise variance, said operations comprising:
computing an error signal based on a difference between a reference voltage and an output voltage of said voltage regulator;
generating a control signal proportional to said error signal;
generating a control signal based on a derivative of said error signal;
summing said proportional control signal and said derivative control signal;
adjusting a PWM modulation of said voltage regulator based on said summed control signal;
determining a state of said output voltage of said voltage regulator; and
adjusting a gain of said proportional control signal and said derivative control signal based on said determined state, wherein said gain of said derivative control signal is decreased a predetermined programmable period of time after said state monitor circuit determines said output voltage entered a steady state.

17. The one or more non-transitory computer-readable memories of claim 16 , wherein said operations further comprise generating a control signal based on an integral of said error signal and summing said integral control signal to said proportional control signal and said derivative control signal.

18. The one or more non-transitory computer-readable memories of claim 16 , wherein said operations further comprise increasing said gain adjustment on said derivative control signal in response to determining that said output voltage enters a transition state.

19. The one or more non-transitory computer-readable memories of claim 16 , wherein said operations further comprise decreasing said gain adjustment on said proportional control signal in response to determining that said output voltage enters a transition state.

20. The one or more non-transitory computer-readable memories of claim 16 , wherein said operations further comprise increasing said gain adjustment on said proportional control signal in response to determining that said output voltage enters said steady state.

21. The one or more non-transitory computer-readable memories of claim 16 , wherein said operations further comprise programming a minimum value of said gain adjustment and a maximum value of said gain adjustment.

22. The one or more non-transitory computer-readable memories of claim 21 , wherein said operations further comprise programming a transition time between said minimum value of said gain adjustment and said maximum value of said gain adjustment.

Assignees

• Ali Isaac
• Cowley Nicholas P
• Intel Corp

Inventors

• Ali Isaac
• Cowley Nicholas P

Classifications

• H02M3/157 Primary

  with digital control · CPC title

• H02M2003/1566

  Electricity · mapped topic

• H02M2001/0025

  Electricity · mapped topic

• H02M3/10 Primary

  using discharge tubes with control electrode or semiconductor devices with control electrode (H02M3/07 takes precedence) · CPC title

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title