Systems, methods, and devices for pulse amplitude modulated charging
US-2024405592-A1 · Dec 5, 2024 · US
US9509211B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9509211-B2 |
| Application number | US-201414499597-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2014 |
| Priority date | Mar 28, 2014 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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A bridgeless power factor improvement converter is configured with input terminals to which an AC voltage is input, output terminals from which a DC voltage is output, diodes, first and second switches, first and second coils, a pair of series diodes, and a control circuit. When one input terminal has a positive potential relative to the other input terminal, the control circuit performs a switching operation for only the first switch. When the one input terminal has a negative potential relative to the other input terminal, the control circuit performs the switching operation for only the second switch. A capacitor, which is provided independently from the pair of series diodes, is connected to at least one of the pair of series diodes in parallel.
Opening claim text (preview).
What is claimed is: 1. A bridgeless power factor improvement converter, comprising: a pair of input terminals to which an AC voltage is input, the pair of input terminals including a first input terminal and a second input terminal; a pair of output terminals from which an output voltage is output, the pair of output terminals including a first output terminal and a second output terminal, the first output terminal having a positive potential relative to the second output terminal; a first rectifier having a first current input terminal and a first current output terminal, the first current output terminal being connected to the first output terminal; a first switch that is connected between the second output terminal and the first current input terminal; a second rectifier having a second current input terminal and a second current output terminal, the second current input terminal being connected to the second output terminal; a second switch that is connected between the first output terminal and the second current output terminal; a first coil that is connected between the first input terminal and a first node connected between the first rectifier and the first switch; a second coil that is connected between the first input terminal and a second node connected between the second rectifier and the second switch; a pair of series rectifiers that are connected in series in a forward direction via a third node and that have a third current input terminal and a third current output terminal that are opposite to each other, the third current output terminal being connected to the first output terminal, the third current input terminal being connected to the second output terminal, the third node being connected to the second input terminal; a capacitor that has first and second capacitor ends that are opposite to each other, the first capacitor end being directly connected to the third node, the second capacitor end being directly connected to one of the third current input terminal and the third current output terminal of the pair of series rectifiers so that the capacitor is serially connected between the third node and one of the third current input terminal and the third current output terminal of the pair of series rectifiers; a pair of output capacitors that are connected in series via a fourth node between the first and second output terminals; a resonance inductor and a first bidirectional switch that are connected in series via a fifth node between the third node and the fourth node; and a control circuit that switches the first and second switches according to the AC voltage, wherein when the first input terminal has a positive potential relative to the second input terminal, the control circuit switches only the first switch, and when the first input terminal has a negative potential relative to the second input terminal, the control circuit switches only the second switch. 2. The bridgeless power factor improvement converter according to claim 1 , wherein the capacitor is provided independently from the pair of series rectifiers. 3. The bridgeless power factor improvement converter according to claim 1 , wherein the control circuit drives the first bidirectional switch so as to be in an ON state in synchronization with a polarity change of the AC voltage during a dead time period between an ON period of the first switch and an ON period of the second switch. 4. The bridgeless power factor improvement converter according to claim 3 , further comprising: a pair of clamping rectifiers that are connected in series in a forward direction via a sixth node and that have a clamping current input terminal and a clamping current output terminal, the clamping current output terminal being connected to the first output terminal, the clamping current input terminal being connected to the second output terminal, the sixth node being connected to the fifth node. 5. The bridgeless power factor improvement converter according to claim 3 , further comprising: a clamping circuit that is connected to the resonance inductor in parallel, wherein the clamping circuit decreases a voltage that is generated between both ends of the resonance inductor. 6. The bridgeless power factor improvement converter according to claim 5 , wherein the clamping circuit is a resistor that is connected to the resonance inductor in parallel. 7. The bridgeless power factor improvement converter according to claim 5 , wherein the clamping circuit is a pair of Zener diodes that are connected in series in an opposite direction to each other and that are connected to the resonance inductor in parallel. 8. The bridgeless power factor improvement converter according to claim 5 , wherein the clamping circuit is a second bidirectional switch that is connected to the resonance inductor in parallel, and the control circuit drives the first bidirectional switch to be in an OFF state from an ON state and concurrently drives the second bidirectional switch to be temporarily in the ON state. 9. The bridgeless power factor improvement converter according to claim 1 , further comprising: a second capacitor that has third and fourth capacitor ends that are opposite to each other, the third capacitor end being directly connected to the third node, the fourth capacitor end being directly connected to the other of the third current input terminal and the third current output terminal of the pair of series rectifiers so that the second capacitor is serially connected between the third node and the other of the third current input terminal and the third current output terminal of the pair of series rectifiers, wherein the capacitor and the second capacitor are serially connected to each other between the third current input terminal and the third current output terminal, and the capacitor and the second capacitor are respectively connected to the pair of series rectifiers in parallel. 10. A bridgeless power factor improvement converter, comprising: a pair of input terminals to which an AC voltage is input, the pair of input terminals including a first input terminal and a second input terminal; a pair of output terminals from which an output voltage is output, the pair of output terminals including a first output terminal and a second output terminal, the first output terminal having a positive potential relative to the second output terminal; a first switch that is connected to the second output terminal; a second switch that is connected between the first switch and the first output terminal so as to be connected with the first switch in series; a coil that is connected between the first input terminal and a first node connected between the first switch and the second switch; a pair of series rectifiers that are connected in series in a forward direction via a second node and that have a first current input terminal and a first current output terminal that are opposite to each other, the first current output terminal being connected to the first output terminal, the first current input terminal being connected to the second output terminal, the second node being connected to the second input terminal; a capacitor that has first and second capacitor ends that are opposite to each other, the first capacitor end being directly connected to the second node, the second capacitor end being directly connected to one of the first current input terminal and the first current output terminal of the pair of series rectifiers so that the capacitor is serially connected between the second node and one of the first current input terminal and the first current output terminal of the pair of series rectifiers; a pair of output capacitors tha
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