Method for manufacturing nano-structured semiconductor light-emitting element

Patent metadata

Field	Value
Publication number	US-9508893-B2
Application number	US-201414764484-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Jan 29, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.

First claim

The invention claimed is:

1. A method for manufacturing a nanostructure semiconductor light emitting device, the method comprising:
forming a mask having a plurality of openings on a base layer;
growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores;
partially removing the mask such that side surfaces of the plurality of nanocores are exposed;
sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures;
forming a contact electrode on surfaces of the plurality of light emitting nanostructures, the contact electrode forming ohmic-contact with the second conductivity-type semiconductor layer;
planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed; and
partially removing the contact electrode such that the contact electrode has a height lower than upper surfaces of the light emitting nanostructures.

2. The method of claim 1 , further comprising heat-treating the plurality of nanocores, between the partially removing of the mask and the sequentially growing of the active layer and the second conductivity-type semiconductor layer.

3. The method of claim 2 , wherein the heat treatment is performed in a temperature range from 600° C. to 1200° C.

4. The method of claim 1 , wherein the plurality of nanocores have a substantially cylindrical shape before the heat treatment, and the shape of the plurality of nanocores are converted into a substantial hexagonal prismatic shape through the heat treatment.

5. The method of claim 1 , wherein the forming of the plurality of nanocores comprises a crystal stabilization operation of performing a heat treatment after temporarily halting growth of the first conductivity-type semiconductor layer during growth of the first conductivity-type semiconductor layer.

6. The method of claim 1 , further comprising forming an insulating layer to fill spaces between the plurality of light emitting nanostructures, after the forming of the contact electrode and prior to the planarizing.

7. The method of claim 1 , wherein side surfaces of the plurality of nanocores have crystal planes perpendicular to an upper surface of the base layer.

8. The method of claim 7 , wherein the plurality of light emitting nanostructures and the base layer are a nitride single crystal, and the side surfaces of the plurality of nanocores are non-polar surfaces.

9. The method of claim 1 , wherein the mask comprises a first material layer positioned on the base layer and a second material layer positioned on the first material layer and having an etching rate greater than that of the first material layer, and the partially removing the mask comprises removing the second material layer such that the first material layer remains.

10. The method of claim 1 , wherein the plurality of openings are classified as belonging to two or more groups different from each other in terms of at least one of a diameter of the plurality of openings and an interval between the plurality of openings, openings of the different groups have substantially the same diameter and interval therebetween, light emitting nanostructures positioned in openings of the different groups emit light having different wavelengths, and light emitting nanostructures positioned in openings of the same group emit light having substantially the same wavelength.

11. The method of claim 10 , wherein light of different wavelengths emitted from light emitting nanostructures positioned in the openings of the different groups are combined to form white light.

12. The method of claim 1 , further comprising: regrowing the plurality of nanocores by supplying a source gas for the first conductivity-type semiconductor, between the partially removing of the mask and the sequentially growing of the active layer and the second conductivity-type semiconductor layer.

13. A method for manufacturing a nanostructure semiconductor light emitting device, the method comprising:
forming a mask having a plurality of openings on a base layer;
growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores;
sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures;
forming a contact electrode on surfaces of the plurality of light emitting nanostructures, the contact electrode forming ohmic-contact with the second conductivity-type semiconductor layer;
planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed; and
partially removing the contact electrode such that the contact electrode has a height lower than upper surfaces of the plurality of light emitting nanostructures.

14. The method of claim 13 , further comprising: forming an insulating layer to fill spaces between the plurality of light emitting nanostructures, between the forming of the contact electrode and the planarizing.

15. A method for manufacturing a nanostructure semiconductor light emitting device, the method comprising:
forming a mask having a plurality of openings on a base layer;
growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores;
sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures;
forming a contact electrode on surfaces of the plurality of light emitting nanostructures;
planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed; and
partially removing the contact electrode such that the contact electrode has a height lower than upper surfaces of the plurality of light emitting nanostructures,
wherein the mask comprises a first material layer positioned on the base layer and a second material layer positioned on the first material layer and having an etching rate greater than that of the first material layer, and
the method further comprising: removing the second material layer to expose side surfaces of the plurality of nanocores such that the first material layer remains, before the forming of the plurality of light emitting nanostructures.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Nam-Goo
• Kim Dong-Ho
• Yoo Geon-Wook

Classifications

• H10H20/8316

  Multi-layer electrodes comprising at least one discontinuous layer · CPC title

• H10H20/8312

  extending at least partially through the bodies · CPC title

• H10H20/034

  of coatings · CPC title

• H10H20/032

  of electrodes · CPC title

• H10H20/01335

  the light-emitting regions comprising nitride materials · CPC title