Schottky diode and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9508873-B2
Application number	US-201414339915-A
Country	US
Kind code	B2
Filing date	Jul 24, 2014
Priority date	Dec 3, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Provided is a Schottky diode. The Schottky diode includes: a substrate; a core on the substrate; a metallic layer on the core; and a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer.

First claim

What is claimed is:

1. A Schottky diode comprising:
a substrate;
a core on the substrate;
a metallic layer on the core; and
a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer,
wherein the core comprises a first semiconductor nanowire, and
wherein the shell comprises a second semiconductor having a different energy band gap from the first semiconductor nanowire and forming a heterojunction structure staggered with the first semiconductor nanowire.

2. The diode of claim 1 , wherein the first semiconductor nanowire extends vertically to the substrate.

3. The diode of claim of 1 , wherein each of the first semiconductor nanowire and the second semiconductor comprises an intrinsic semiconductor.

4. The diode of claim 1 , wherein the second semiconductor comprises an intrinsic silicon nanowire.

5. The diode of claim 1 , wherein the first semiconductor nanowire comprises an intrinsic germanium nanowire.

6. The diode of claim 1 , wherein the first semiconductor nanowire comprises an intrinsic germanium nanowire or an intrinsic silicon nanowire of which Fermi energy level is adjusted by the surface pinning effect or the surface Fermi energy pinning effect.

7. The diode of claim 1 , further comprising at least one insulating interlayer disposed between the metallic layer and the substrate to surround the shell.

8. The diode of claim 7 , wherein the insulating interlayer comprises a first insulating layer surrounding a sidewall of the shell and a second insulating layer surrounding a sidewall of the first insulating layer.

9. The diode of claim 1 , wherein the metallic layer extends from a top of the core and the shell to an external sidewall of the shell.

10. The diode of claim 1 , further comprising an interfacial layer disposed between the core and the metallic layer.

11. A Schottky diode comprising:
a substrate;
a core on the substrate;
a metallic layer on the core; and
a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer,
wherein the metallic layer comprises:
a first metallic layer on the core and the shell; and
a second metallic layer on the first metallic layer,
wherein the first metallic layer forms the Schottky junction with respect to the core and the shell.

12. A method of fabricating a Schottky diode, the method comprising:
forming a core on a substrate;
forming a shell surrounding the core; and
forming a metallic layer on the shell and the core,
wherein the core forms a Schottky junction with the metallic layer by adjusting a Fermi energy level through the shell and the core is not doped with an impurity
wherein the core comprises a first semiconductor nanowire, and
wherein the shell comprises a second semiconductor having a different energy band gap from the first semiconductor nanowire and forming a heterojunction structure staggered with the first semiconductor nanowire.

13. The method of claim 12 , wherein the first semiconductor nanowire is formed through a vapor-liquid-solid (VLS) growth method.

14. The method of claim 12 , wherein the second semiconductor is formed through a chemical vapor deposition method or an atomic layer deposition method.

15. The method of claim 12 , further comprising forming an insulating interlayer surrounding the shell.

Assignees

• Electronics & Telecommunications Res Inst
• Univ Michigan Regents
• Nat Science Found

Inventors

• Suh Dongwoo
• Kim Young Jun
• Lu Wei
• Chen Lin

Classifications

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D8/051

  of Schottky diodes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/205

  Nanosized electrodes, e.g. nanowire electrodes · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title