Method for manufacturing semiconductor device and pin diode

Patent metadata

Field	Value
Publication number	US-9508872-B2
Application number	US-201314888163-A
Country	US
Kind code	B2
Filing date	Jul 11, 2013
Priority date	Jul 11, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An IGBT ( 15 ) is formed in a semiconductor substrate ( 1 ). A temperature sense diode ( 17 ) made of polysilicon or amorphous silicon is formed on the semiconductor substrate ( 1 ). After forming the IGBT ( 15 ), the temperature sense diode ( 17 ) is divided into a plurality of diodes by selectively oxidizing or sublimating part of the temperature sense diode ( 17 ). Thus, influences of variations in finished dimension of polysilicon on the characteristics can be eliminated. As a result, it is possible to reduce the size while reducing characteristic variations.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device comprising:
forming a transistor in a semiconductor substrate;
forming a PIN diode made of polysilicon or amorphous silicon on the semiconductor substrate; and
after forming the transistor, selectively oxidizing or sublimating part of the PIN diode to divide the PIN diode into a plurality of diodes.

2. The method for manufacturing a semiconductor device of claim 1 , further comprising performing re-crystallization, oxidization, or change of grain size by selectively applying heat treatment to part of the plurality of diodes.

3. The method for manufacturing a semiconductor device of claim 2 , wherein an n-type layer of the PIN diode is selectively re-crystalized.

4. The method for manufacturing a semiconductor device of claim 2 , wherein an i-type layer of the PIN diode is selectively re-crystalized.

5. The method for manufacturing a semiconductor device of claims 2 , wherein a p-type layer of the PIN diode is selectively re-crystalized.

6. The method for manufacturing a semiconductor device of claim 2 , wherein a bonding region between an n-type layer and an i-type layer, and a bonding region between a p-type layer and the i-type layer of the PIN diode are selectively re-crystalized.

7. The method for manufacturing a semiconductor device of claim 2 , wherein a region excluding a bonding region between an n-type layer and an i-type layer and a bonding region between a p-type layer and the i-type layer of the PIN diode is selectively re-crystalized.

8. The method for manufacturing a semiconductor device of claim 2 , wherein an upper layer part of the PIN diode is selectively re-crystalized.

9. The method for manufacturing a semiconductor device of claim 2 , wherein an upper layer part of the PIN diode is selectively oxidized.

10. The method for manufacturing a semiconductor device of claim 9 , wherein an upper layer part of a p-type layer and an upper layer part of an n-type layer of the PIN diode are selectively oxidized.

11. The method for manufacturing a semiconductor device of claim 9 , wherein an upper layer part of an i-type layer of the PIN diode is selectively oxidized.

12. The method for manufacturing a semiconductor device of claim 9 , wherein an upper layer part of a region excluding a bonding region between an n-type layer and an i-type layer and a bonding region between a p-type layer and the i-type layer of the PIN diode is selectively oxidized.

13. A PIN diode wherein the PIN diode is made of polysilicon or amorphous silicon, and
part of the PIN diode is selectively oxidized or sublimated so that the PIN diode is divided into a plurality of diodes.

14. The PIN diode of claim 13 , wherein re-crystallization, oxidization, or change of grain size is selectively performed in part of the plurality of diodes.

Assignees

• Mitsubishi Electric Corp

Inventors

• Fujii Hidenori

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title