Semiconductor device

Patent metadata

Field	Value
Publication number	US-9508861-B2
Application number	US-201414272742-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 16, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a transistor comprising:
a first gate electrode;
a first gate insulating film over the first gate electrode;
a first oxide semiconductor film over a first region of the first gate insulating film;
a source electrode and a drain electrode over the first oxide semiconductor film;
a second gate insulating film over the first oxide semiconductor film, the source electrode, and the drain electrode;
a second gate electrode over the second gate insulating film;
the second gate electrode in direct contact with a second region of the first gate insulating film; and
a third electrode in direct contact with the first gate insulating film and one of the source electrode and the drain electrode,

wherein the first oxide semiconductor film is located between the first gate electrode and the second gate electrode,
wherein the second gate electrode comprises a first region and a second region that face each other in a channel width direction of the transistor,
wherein the first oxide semiconductor film is located between the first region and the second region of the second gate electrode,
wherein the first oxide semiconductor film comprises indium and zinc,
wherein the first oxide semiconductor film comprises a crystalline region,
wherein the second gate electrode comprises a metal oxide,
wherein the third electrode comprises the metal oxide, and
wherein a thickness of the first region of the first gate insulating film is larger than that of the second region of the first gate insulating film.

2. The semiconductor device according to claim 1 , wherein the second gate electrode is in contact with a side surface of the second gate insulating film.

3. The semiconductor device according to claim 1 , wherein a side surface of the first oxide semiconductor film faces the second gate electrode in the channel width direction of the transistor.

4. The semiconductor device according to claim 1 , wherein the second gate insulating film is in contact with the first gate insulating film.

5. The semiconductor device according to claim 1 , wherein the second gate electrode is electrically connected to the first gate electrode through a contact hole provided in the first gate insulating film.

6. The semiconductor device according to claim 1 ,
wherein the second gate electrode is electrically connected to the first gate electrode through a first contact hole and a second contact hole each provided in the first gate insulating film, and
wherein the first oxide semiconductor film is located between the first contact hole and the second contact hole.

7. The semiconductor device according to claim 1 , wherein an outline of the first oxide semiconductor film is located inside an outline of the first gate electrode.

8. The semiconductor device according to claim 1 , wherein the second gate insulating film comprises:
a first oxide insulating film;
a second oxide insulating film over the first oxide insulating film; and
a nitride insulating film over the second oxide insulating film.

9. The semiconductor device according to claim 1 ,
wherein the transistor comprises:
a second oxide semiconductor film over the first gate insulating film; and
a third oxide semiconductor film over the first oxide semiconductor film,

wherein the first oxide semiconductor film is located between the second oxide semiconductor film and the third oxide semiconductor film,
wherein the source electrode and the drain electrode is located over the third oxide semiconductor film, and
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film comprises indium, gallium, and zinc.

10. The semiconductor device according to claim 1 , wherein the transistor is provided over a substrate.

11. A display device comprising:
a pixel portion comprising:
a transistor comprising:
a first gate electrode;
a first gate insulating film over the first gate electrode;
a first oxide semiconductor film over a first region of the first gate insulating film;
a first electrode and a second electrode over the first oxide semiconductor film;
a second gate insulating film over the first oxide semiconductor film, the first electrode, and the second electrode;
a second gate electrode over the second gate insulating film;
the second gate electrode in direct contact with a second region of the first gate insulating film; and
a third electrode in direct contact with the first gate insulating film and the first electrode,

wherein the first oxide semiconductor film is located between the first gate electrode and the second gate electrode,
wherein the second gate electrode comprises a first region and a second region that face each other in a channel width direction of the transistor,
wherein the first oxide semiconductor film is located between the first region and the second region of the second gate electrode,
wherein the first oxide semiconductor film comprises indium and zinc,
wherein the first oxide semiconductor film comprises a crystalline region,
wherein the second gate electrode comprises a metal oxide,
wherein the third electrode comprises the metal oxide, and
wherein a thickness of the first region of the first gate insulating film is larger than that of the second region of the first gate insulating film.

12. The display device according to claim 11 , wherein the second gate electrode is in contact with a side surface of the second gate insulating film.

13. The display device according to claim 11 , wherein a side surface of the first oxide semiconductor film faces the second gate electrode in the channel width direction of the transistor.

14. The display device according to claim 11 , wherein the second gate insulating film is in contact with the first gate insulating film.

15. The display device according to claim 11 , wherein the second gate electrode is electrically connected to the first gate electrode through a contact hole provided in the first gate insulating film.

16. The display device according to claim 11 ,
wherein the second gate electrode is electrically connected to the first gate electrode through a first contact hole and a second contact hole each provided in the first gate insulating film, and
wherein the first oxide semiconductor film is located between the first contact hole and the second contact hole.

17. The display device according to claim 11 , wherein an outline of the first oxide semiconductor film is located inside an outline of the first gate electrode.

18. The display device according to claim 11 , wherein the second gate insulating film comprises:
a first oxide insulating film;
a second oxide insulating film over the first oxide insulating film; and
a nitride insulating film over the second oxide insulating film.

19. The display device according to claim 11 ,
wherein the transistor comprises:
a second oxide semiconductor film over the first gate insulating film; and
a third oxide semiconductor film over the first oxide semiconductor film,

wherein the first oxide semiconductor film is located between the second oxide semiconductor film and the third oxide semiconductor film,
wherein the first electrode and the second electrode is located over the third oxide semiconductor film, and
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film comprises indium, gallium, and zinc.

20. The di

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Miyake Hiroyuki
• Okazaki Kenichi
• Hayakawa Masahiko
• Matsuda Shinpei

Classifications

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title