Method and system for a semiconductor device with integrated transient voltage suppression

Patent metadata

Field	Value
Publication number	US-9508841-B2
Application number	US-201313957115-A
Country	US
Kind code	B2
Filing date	Aug 1, 2013
Priority date	Aug 1, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

First claim

The invention claimed is:

1. A power transistor assembly with integrated transient voltage suppression on a single semiconductor substrate comprising:
a transistor formed of a wide band gap material, said transistor comprising the single semiconductor substrate of a first polarity, a drift layer of a second polarity epitaxially grown on the substrate, a gate terminal, a source terminal, and a drain terminal, said transistor further comprising a predetermined maximum allowable gate voltage and drain voltage value; and
a transient voltage suppression (TVS) device formed of a wide band gap material, said TVS device formed with the transistor as a single semiconductor device, said TVS device electrically coupled to said transistor between at least one of said gate and source terminals and said drain and source terminals, said TVS device including a turn-on voltage selected to be less than the predetermined maximum electrical terminal voltage value, wherein said TVS device comprises silicon carbide (SiC) and is formed by ions implanted on a surface of said drift layer.

2. The assembly of claim 1 , wherein said transistor comprises silicon carbide (SiC).

3. The assembly of claim 1 , wherein said transistor comprises a metal oxide semiconductor (MOS) transistor.

4. The assembly of claim 1 , wherein said transistor and said TVS device are formed as a single semiconductor circuit.

5. The assembly of claim 1 , wherein said transistor and said TVS device are formed as separate devices on a monolithic semiconductor die and coupled electrically using metallic traces between terminals of said transistor and said TVS.

6. The assembly of claim 1 , wherein said TVS device comprises a plurality of TVS device circuits electrically coupled in at least one of electrical parallel, electrical series, and a combination thereof.

7. The assembly of claim 1 , wherein said TVS device comprises layers of doped semiconductor material and wherein the layers are stacked laterally within one or more layers of epitaxy.

8. The assembly of claim 1 , wherein said TVS device comprises layers of doped semiconductor material and wherein the layers are stacked vertically using a plurality of layers.

9. A power transistor assembly with integrated transient voltage suppression on a single semiconductor substrate comprising:
a transistor formed of a wide band gap material, said transistor comprising the single semiconductor substrate of a first polarity, a drift layer of a second polarity epitaxially grown on the substrate, a gate terminal, a source terminal, and a drain terminal, said transistor further comprising a predetermined maximum allowable gate voltage and drain voltage value; and
a transient voltage suppression (TVS) device formed of a wide band gap material, said TVS device formed with the transistor as a single semiconductor device, said TVS device electrically coupled to said transistor between at least one of said gate and source terminals and said drain and source terminals, said TVS device including a turn-on voltage selected to be less than the predetermined maximum electrical terminal voltage value, wherein said TVS device comprises silicon carbide (SiC) and is formed by ions implanted on a surface of said drift layer, wherein said TVS device comprises at least a three-layer structure and operates only using punch-through physics, avalanche, or combinations thereof.

10. A transient voltage protected transistor system comprising:
a field effect transistor (FET) comprising:
a silicon carbide semiconductor substrate formed of a first conductivity type material and a first polarity; and
an epitaxial drift layer formed of a silicon carbide semiconductor material of a second polarity that is relatively lightly doped with respect to the substrate; and
a transient voltage suppression (TVS) device formed of silicon carbide semiconductor material, said TVS electrically coupled to said transistor between at least one of said gate and source terminals and said drain and source terminals, said TVS device formed by implanted ions in a portion of the drift layer.

11. The system of claim 10 , wherein said TVS device and the transistor comprise a single semiconductor device formed on a single semiconductor die.

12. The system of claim 10 , wherein said TVS device and said transistor comprise separate semiconductor devices formed on a single semiconductor die.

13. The system of claim 10 , wherein said TVS device and said transistor comprise separate semiconductor devices formed on separate semiconductor dies and electrically coupled in a package.

14. The system of claim 10 , wherein said TVS device comprises a plurality of TVS circuits electrically coupled in at least one of electrical parallel, electrical series, or combinations thereof.

15. The system of claim 10 , wherein said TVS device further comprises a third layer of semiconductor material implanted with ions having the first polarity, the layers extending laterally across a face of said FET.

16. The assembly of claim 9 , wherein said transistor comprises silicon carbide (SiC).

17. The assembly of claim 9 , wherein said transistor comprises a metal oxide semiconductor (MOS) transistor.

18. The assembly of claim 9 , wherein said transistor and said TVS device are formed as a single semiconductor circuit.

19. The assembly of claim 9 , wherein said transistor and said TVS device are formed as separate devices on a monolithic semiconductor die and coupled electrically using metallic traces between terminals of said transistor and said TVS.

20. The assembly of claim 9 , wherein said TVS device comprises a plurality of TVS device circuits electrically coupled in at least one of electrical parallel, electrical series, and a combination thereof.

21. The assembly of claim 9 , wherein said TVS device comprises layers of doped semiconductor material and wherein the layers are stacked laterally within one or more layers of epitaxy.

22. The assembly of claim 9 , wherein said TVS device comprises layers of doped semiconductor material and wherein the layers are stacked vertically using a plurality of layers.

Assignees

• Gen Electric

Inventors

• Kashyap Avinash Srikrishnan
• Sandvik Peter Micah
• Mcmahon James Jay
• Stevanovic Ljubisa Dragoljub

Classifications

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D18/00

  Thyristors · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D89/611

  using diodes as protective elements · CPC title