Trench capacitors and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9508790-B2
Application number	US-201514724437-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Feb 24, 2012
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having an opening comprising a first sidewall;
a central pillar disposed in a central region of the opening, the central pillar comprising a first electrode material;
a first dielectric layer disposed around the central pillar;
a second electrode material disposed around the first dielectric layer, the second electrode material contacting a first portion of the first sidewall;
a peripheral pillar disposed in a periphery region of the opening, the peripheral pillar electrically coupled to the central pillar; and
a second dielectric layer disposed around the peripheral pillar, the second dielectric layer contacting a second portion of the first sidewall.

2. The device of claim 1 , wherein the central pillar and the peripheral pillar form part of a first electrode of a trench capacitor, the first and the second dielectric layers form part of a capacitor dielectric of the trench capacitor, and the second electrode material form part of a second electrode of the trench capacitor.

3. The device of claim 1 , wherein the peripheral pillar comprises the first electrode material.

4. The device of claim 1 , wherein the second electrode material is disposed partially around the second dielectric layer.

5. The device of claim 1 , wherein the peripheral pillar has a faceted shape.

6. The device of claim 5 , wherein the peripheral pillar has a sidewall oriented along a {100} or a {110} crystal plane of the substrate.

7. The device of claim 1 , wherein the central pillar has a faceted shape.

8. The device of claim 1 , wherein the first portion of the first sidewall is a central portion of the first sidewall, and wherein the second portion of the first sidewall is nearer to an edge of the first sidewall than the first portion.

9. The device of claim 1 , wherein the first portion of the first sidewall is nearer to an edge of the first sidewall than the second portion, and wherein the second portion of the first sidewall is a central portion of the first sidewall.

10. The device of claim 1 , wherein the opening comprises a second sidewall, the second sidewall being perpendicular to the first sidewall.

11. The device of claim 1 , wherein the substrate is capacitively coupled through the second portion of the first sidewall.

12. The device of claim 1 , further comprising a doped region disposed in the substrate around the opening.

13. The device of claim 1 , wherein the substrate comprises silicon, and the second electrode material comprises mono-crystalline silicon.

14. A semiconductor device comprising:
a semiconductor substrate having an opening comprising a first sidewall;
a central pillar disposed in a central region of the opening, the central pillar comprising a first electrode material;
a first dielectric layer disposed around the central pillar;
a second electrode material disposed around the first dielectric layer, the second electrode material contacting a first portion of the first sidewall but not contacting all of the first sidewall; and
a peripheral pillar comprising a semiconductor material of the semiconductor substrate disposed in a periphery region of the opening, the peripheral pillar electrically coupled to the central pillar.

15. The device of claim 14 , further comprising:
a second dielectric layer disposed around the peripheral pillar, the second dielectric layer contacting a second portion of the first sidewall, wherein the second electrode material covers a remaining portion of the second dielectric layer.

16. The device of claim 15 , wherein a sidewall of the peripheral pillar is oriented along a {100} or a {110} crystal plane of the semiconductor substrate.

17. The device of claim 14 , wherein the substrate comprises silicon, and the second electrode material comprises mono-crystalline silicon.

18. A semiconductor device comprising:
an opening comprising a first sidewall disposed in a substrate;
a central pillar disposed in a central region of the opening, the central pillar comprising a first electrode material;
a first dielectric layer disposed around the central pillar;
a second electrode material disposed around the first dielectric layer, the second electrode material contacting a first portion of the first sidewall but not contacting all of the first sidewall; and
a peripheral pillar disposed in a periphery region of the opening, the peripheral pillar electrically coupled to the central pillar.

19. The device of claim 18 , further comprising a second dielectric layer disposed around the peripheral pillar, the second dielectric layer contacting a second portion of the first sidewall, wherein the second electrode material covers a remaining portion of the second dielectric layer.

20. The device of claim 18 , wherein a sidewall of the peripheral pillar is oriented along a {100} or a {110} crystal plane of the substrate.

21. The device of claim 18 , wherein the substrate comprises silicon, and the second electrode material comprises mono-crystalline silicon.

Assignees

• Infineon Technologies Ag

Inventors

• Popp Thomas
• Pompl Stefan
• Berger Rudolf

Classifications

• H10D84/212

  of only capacitors · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L27/0805

  Electricity · mapped topic

• H01L28/90 Primary

  Electricity · mapped topic