Display device and electronic equipment

US9508780B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9508780-B2
Application numberUS-201514826277-A
CountryUS
Kind codeB2
Filing dateAug 14, 2015
Priority dateAug 15, 2007
Publication dateNov 29, 2016
Grant dateNov 29, 2016

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a pixel array section, the pixel array section having pixels arranged in a matrix form, at least one of the pixels including an electro-optical element, a write transistor, a capacitor, a drive transistor, and a switching transistor. A write scan line is disposed for each pixel row of the pixel array section and adapted to convey a write signal to be applied to a gate electrode of the write transistor. The wiring structure of the write scan line does not cross a wiring pattern connected to a gate electrode of the drive transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a plurality of pixels arranged in a matrix form, at least one of the plurality of pixels including: an electro-optical element; a first capacitor; a second capacitor; a drive transistor configured to drive the electro-optical element; a sampling transistor configured to apply a data signal from a data line to a first terminal of the first capacitor; a first switching transistor connected between a first voltage line and the drive transistor; and a second switching transistor connected between a second voltage line and a second terminal of the first capacitor, wherein a control terminal of the sampling transistor is connected to a first scan line, wherein a control terminal of the first switching transistor is connected to a second scan line, wherein a control terminal of the second switching transistor is connected to a third scan line, wherein the first scan line, the second scan line, and the third scan line extend along a first direction, wherein the data line and the first voltage line extend along a second direction perpendicular to the first direction, wherein the second capacitor includes a first terminal connected to the first voltage line, and a second terminal connected to the second terminal of the first capacitor, wherein the sampling transistor is connected to the first terminal of the first capacitor through a first wiring, and wherein each of the first scan line and the second scan line is not crossing the first wiring. 2. The display device according to claim 1 , wherein the first capacitor and the second capacitor are arranged between the first scan line and third scan line. 3. The display device according to claim 1 , wherein the first scan line, the second scan line, and the third scan line include Molybdenum, and wherein the data line and the first voltage line include Aluminum. 4. The display device according to claim 3 , wherein the first wiring includes Aluminum. 5. The display device according to claim 1 , further comprising a third switching transistor connected between a third voltage line and the first terminal of the first capacitor, wherein the third voltage line extends along the second direction. 6. A display device comprising: a plurality of pixels arranged in a matrix form, at least one of the plurality of pixels including: an electro-optical element; a drive transistor configured to drive the electro-optical element; a sampling transistor configured to connect a data line to a control terminal of the drive transistor; a first switching transistor configured to connect a first voltage line to a first terminal of the drive transistor; a second switching transistor configured to connect a second voltage line to a second terminal of the drive transistor; a first capacitor; and a second capacitor, wherein a first terminal of the first capacitor is connected to the control terminal of the drive transistor, wherein a second terminal of the first capacitor is connected to the second terminal of the drive transistor, wherein a first terminal of the second capacitor is connected to the second terminal of the drive transistor, wherein a control terminal of the sampling transistor is connected to a first scan line, wherein a control terminal of the first switching transistor is connected to a second scan line, wherein a control terminal of the second switching transistor is connected to a third scan line, wherein the sampling transistor is connected to the first terminal of the first capacitor through a first wiring, and wherein each of the first scan line and the second scan line is not crossing the first wiring. 7. The display device according to claim 6 , wherein the first capacitor and the second capacitor are arranged between the first scan line and third scan line. 8. The display device according to claim 6 , wherein the first scan line, the second scan line, and the third scan line include Molybdenum, and wherein the data line and the first voltage line include Aluminum. 9. The display device according to claim 8 , wherein the first wiring includes Aluminum. 10. The display device according to claim 6 , further comprising a third switching transistor connected between a third voltage line and the first terminal of the first capacitor, wherein the third voltage line extends along the second direction.

Assignees

Inventors

Classifications

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • forming a linear amplifier or follower · CPC title

  • using an active matrix · CPC title

  • Layout of electrodes and connections · CPC title

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Frequently asked questions

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What does patent US9508780B2 cover?
A display device includes a pixel array section, the pixel array section having pixels arranged in a matrix form, at least one of the pixels including an electro-optical element, a write transistor, a capacitor, a drive transistor, and a switching transistor. A write scan line is disposed for each pixel row of the pixel array section and adapted to convey a write signal to be applied to a gate …
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).