Memory system, semiconductor device and fabrication method therefor
US-2024107759-A1 · Mar 28, 2024 · US
Semiconductor device and method of fabricating the same
US9508737B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9508737-B2 |
| Application number | US-201414539140-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 12, 2014 |
| Priority date | Mar 31, 2014 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: forming a molding structure on a substrate, the molding structure including insulating layers and sacrificial layers that are alternately and repeatedly stacked on the substrate; forming a plurality of vertical channel structures penetrating the molding structure, each of the vertical channel structures including a first vertical channel pattern on the substrate, and a second vertical channel pattern on the first vertical channel pa…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L27/11582Primary
Electricity · mapped topic
Electricity · mapped topic
- H10B41/27Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9508737B2 cover?
- Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gat…
- Who is the assignee on this patent?
- Kim Jung-Hwan, Yang Hanvit, Noh Jintae, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).