Three-dimensional charge trapping NAND cell with discrete charge trapping film

Patent metadata

Field	Value
Publication number	US-9508736-B2
Application number	US-201314056577-A
Country	US
Kind code	B2
Filing date	Oct 17, 2013
Priority date	Oct 17, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
a substrate;
a plurality of insulating layers;
a plurality of second functional elements interleaved with the plurality of insulating layers, inner walls of the plurality of insulating layers and the plurality of second functional elements defining a channel hole, and each second functional element and adjacent insulating layers defining a recess;
a first functional element disposed in the channel h…

Assignees

• Cypress Semiconductor Corp

Inventors

• Chen Chun
• Chang Kuo-Tung
• Fang Shenqing

Classifications

• H10P50/283

  Electricity · mapped topic

• H10D30/693

  Electricity · mapped topic

• H10D30/0413 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic