Stacked dies with wire bonds and method

Patent metadata

Field	Value
Publication number	US-9508703-B2
Application number	US-201414543760-A
Country	US
Kind code	B2
Filing date	Nov 17, 2014
Priority date	Apr 30, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first die;
a second die attached to the first die;
a third die attached to the second die and located on an opposite side of the second die than the first die;
wire bonds electrically connecting the third die to the first die;
an encapsulant encapsulating the second die and the third die and in physical contact with a first surface of the first die; and
first external connections extending into the encapsulant and in electrical connection with the third die, wherein the first external connections comprise solder extending into the encapsulant.

2. The semiconductor device of claim 1 , wherein the first external connections further comprise:
a copper pillar; and
a conductive cap on the copper pillar, wherein the solder is on the conductive cap.

3. The semiconductor device of claim 1 , wherein the second die is electrically connected to the wire bonds with through substrate vias that extend through the third die.

4. The semiconductor device of claim 1 , wherein the second die is electrically connected to the first die with second wire bonds.

5. The semiconductor device of claim 1 , wherein the first external connections further comprise a conductive bump, the conductive bump extending into the encapsulant and in physical connection with the third die.

6. The semiconductor device of claim 1 , wherein the first die and the second die are in a face-to-face configuration.

7. The semiconductor device of claim 1 , wherein the first die and the second die are in a face-to-back configuration.

8. The semiconductor device of claim 1 , wherein the first die and the third die are in a face-to-face configuration.

9. The semiconductor device of claim 1 , wherein the first die and the third die are in a face-to-back configuration.

10. A semiconductor device comprising:
a first die;
a second die attached to the first die;
a third die attached to the second die and located on an opposite side of the second die than the first die;
wire bonds electrically connecting the third die to the first die;
an encapsulant encapsulating the second die and the third die and in physical contact with a first surface of the first die; and
first external connections extending into the encapsulant and in electrical connection with the third die, wherein the first external connections comprise:
a copper pillar;
a conductive cap on the copper pillar; and
a conductive material on the conductive cap.

11. The semiconductor device of claim 10 , wherein the second die is electrically connected to the wire bonds with through substrate vias that extend through the third die.

12. The semiconductor device of claim 10 , wherein the second die is electrically connected to the first die with second wire bonds.

13. The semiconductor device of claim 10 , wherein the first external connections further comprise a conductive bump, the conductive bump extending into the encapsulant and in physical connection with the third die.

14. A semiconductor device comprising:
a first die;
a second die attached to the first die;
a third die attached to the second die and located on an opposite side of the second die than the first die;
wire bonds electrically connecting the third die to the first die, wherein the second die is electrically connected to the wire bonds with through substrate vias that extend through the third die;
an encapsulant encapsulating the second die and the third die and in physical contact with a first surface of the first die; and
first external connections extending into the encapsulant and in electrical connection with the third die.

15. The semiconductor device of claim 14 , wherein the first external connections comprise solder extending into the encapsulant.

16. The semiconductor device of claim 14 , wherein the first external connections further comprise:
a copper pillar;
a conductive cap on the copper pillar; and
a conductive material on the conductive cap.

17. The semiconductor device of claim 14 , wherein the first external connections further comprise:
a conductive pillar that is planar with an outer surface of the encapsulant; and
a conductive bump in physical connection with the conductive pillar.

18. The semiconductor device of claim 14 , wherein the second die is electrically connected to the first die with second wire bonds.

19. The semiconductor device of claim 14 , wherein the first external connections further comprise a conductive bump, the conductive bump extending into the encapsulant and in physical connection with the third die.

20. The semiconductor device of claim 14 , wherein the encapsulant has a first sidewall, the first die has a second sidewall, and the first sidewall is planar with the second sidewall.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chen Ming-Fa
• Yeh Sung-Feng
• Chen Meng-Tse
• Huang Hui-Min
• Lin Hsiu-Jen
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title