Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US9508699B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9508699-B2 |
| Application number | US-201414466921-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 22, 2014 |
| Priority date | Apr 17, 2014 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.
Opening claim text (preview).
What is claimed is: 1. A semiconductor package comprising: an interposer body having a first surface and a second surface opposite to the first surface; a passivation layer disposed on the first surface of the interposer body; a thermal expansion reinforcing pattern disposed on the second surface of the interposer body; a plurality of through-silicon vias (TSVs) penetrating the interposer body and the thermal expansion reinforcing pattern using a single layer so that one par…
Electricity · mapped topic
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