Low cost hybrid high density package

Patent metadata

Field	Value
Publication number	US-9508687-B2
Application number	US-201514628894-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	Aug 24, 2011
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

First claim

The invention claimed is:

1. A method of making a microelectronic assembly comprising:
electrically joining some contacts of a substrate to respective first lead fingers of a lead frame, the substrate contacts facing the first lead fingers to which they are joined, the substrate having a plurality of the contacts at a first surface and a plurality of terminals at a second surface opposed to the first surface;
aligning and joining element contacts at a front face of a first microelectronic element with corresponding substrate contacts underlying the element contacts;
electrically interconnecting contacts at a face of a second microelectronic element facing away from the substrate with second lead fingers of the lead frame;
forming a common interface for electrical interconnection to a component external to the microelectronic assembly along the second surface of the substrate and the bottom surface of the first lead fingers;
aligning a bottom surface of the first lead fingers with the second surface of the substrate so that the bottom surface of the first lead fingers and the bottom surface of the substrate are coplanar and extend along a common plane parallel to a plane along which the front face of the first microelectronic element extends, the common interface being formed along the plane; and
forming an encapsulant over the first and second microelectronic elements, exposed surfaces of the substrate and over the electrical connections between the second microelectronic element and the second lead fingers.

2. The method as claimed in claim 1 , wherein a plurality of conductive vias and circuitry electrically connect the terminals with the contacts.

3. The method as claimed in claim 1 , wherein a carrier is used to support the substrate and the first lead fingers.

4. The method as claimed in claim 3 , wherein the carrier is removed after the step of forming an encapsulant.

5. The method of claim 1 , wherein forming the encapsulant further comprises forming the encapsulant between the substrate and the first lead fingers, the encapsulant having a bottom surface formed along the plane.

6. The method of claim 1 , further comprising forming the electrical connections between the second microelectronic element and the first lead fingers with wire bonds.

7. The method of claim 1 , wherein forming the encapsulant comprises molding the encapsulant to have a planar surface overlying at least a portion of the second microelectronic element.

8. A method of making a microelectronic assembly comprising:
electrically interconnecting contacts of a substrate with respective first lead fingers of a lead frame, the first lead fingers overlying the substrate contacts to which they are joined, the substrate having a plurality of the contacts at a first surface and a plurality of the terminals at a second surface opposed to the first surface;
electrically connecting element contacts at a front face of a first microelectronic element with corresponding substrate contacts disposed at the first surface of the substrate;
electrically interconnecting contacts at a face of a second microelectronic element and second lead fingers of the lead frame with wirebonds extending therebetween;
aligning a bottom surface of the substrate with a bottom surface of the lead frame so that the bottom surfaces of the substrate and lead frame are coplanar and form a common interface for electrical interconnection to a component external to the microelectronic assembly along the second surface of the substrate and the bottom surface of the lead frame; and
encapsulating the first and second microelectronic elements, exposed surfaces of the substrate, and the wirebonds extending between the second microelectronic element and the second lead fingers.

9. The method of claim 8 , wherein the bottom surfaces of the lead frame and substrate extend along a common plane parallel to a plane along which the front face of the first microelectronic element extends.

10. The method of claim 8 , further comprising positioning a third microelectronic element between the first and second microelectronic elements, element contacts of the third microelectronic element being electrically interconnected with rear contacts disposed at the rear face of the first microelectronic element.

11. The method of claim 8 , further comprising positioning a third microelectronic element between the first and second microelectronic elements, and electrically connecting contacts disposed at a front face of the third microelectronic element with the first lead fingers and the second lead fingers.

12. The method of claim 11 , further comprising electrically interconnecting the contacts of the third microelectronic element with the first and second lead fingers using wirebonds.

13. A method of manufacturing a microelectronic assembly comprising:
positioning a substrate on a carrier layer, the substrate having contacts disposed at a top surface and terminals disposed at an opposed bottom surface;
joining contacts of first lead fingers of a lead frame with the contacts disposed at the top surface of the substrate;
positioning a first microelectronic element so that element contacts disposed at a front face of the first microelectronic element face the contacts disposed at the top surface of the substrate;
positioning a second microelectronic element so that a rear face of the second microelectronic element faces the rear surface of the first microelectronic element, the rear face of the first microelectronic element being opposed to the front face;
aligning a bottom surface of the first lead fingers with the bottom surface of the substrate on the carrier layer so that the bottom surface of the first lead fingers and the bottom surface of the substrate are coplanar and extend along a common plane parallel to a plane along which the front face of the first microelectronic element extends, the common interface being formed along the plane; and
electrically interconnecting the second microelectronic element with the substrate contacts through the first lead fingers.

14. The method of claim 13 , further comprising encapsulating exposed portions of the first and second microelectronic elements and the lead frame.

15. The method of claim 14 , further comprising removing the carrier layer to expose the bottom surface of the substrate.

16. The method of claim 14 , further comprising forming a common interface for electrical interconnection to a component external to the microelectronic assembly along the bottom surface of the substrate and the bottom surface of the first lead fingers.

Assignees

• Tessera Inc

Inventors

• DESAI Kishor
• Low Qwai H
• Chia Chok J
• Woychik Charles G
• Wei Huailiang

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title