Semiconductor device including semiconductor chips stacked via relay substrate

US9508670B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9508670-B2
Application numberUS-201414517993-A
CountryUS
Kind codeB2
Filing dateOct 20, 2014
Priority dateNov 8, 2013
Publication dateNov 29, 2016
Grant dateNov 29, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a support body provided with a wiring layer that includes a first pad; a first semiconductor chip; a first relay substrate stacked on the first semiconductor chip through a first non-conductive adhesion layer and including a first conductive portion and a first protruding electrode electrically connected to the first conductive portion; a second semiconductor chip stacked on the first relay substrate through a second non-conductive adhesion layer, the first protruding electrode of the first relay substrate penetrating the second non-conductive adhesion layer to be connected to the second semiconductor chip; and a first metal wire formed at the first relay substrate to be connected to the first conductive portion for electrically connecting the first conductive portion with the first pad of the wiring layer of the support body.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a support body provided with a wiring layer that includes a first pad; a first semiconductor chip stacked on the support body; a first relay substrate stacked on the first semiconductor chip through a first non-conductive adhesion layer and including a first conductive portion and a first protruding electrode that is electrically connected to the first conductive portion; a second semiconductor chip, provided with a c…

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What does patent US9508670B2 cover?
A semiconductor device includes a support body provided with a wiring layer that includes a first pad; a first semiconductor chip; a first relay substrate stacked on the first semiconductor chip through a first non-conductive adhesion layer and including a first conductive portion and a first protruding electrode electrically connected to the first conductive portion; a second semiconductor chi…
Who is the assignee on this patent?
Shinko Electric Ind Co
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).