Formation of solder and copper interconnect structures and associated techniques and configurations

Patent metadata

Field	Value
Publication number	US-9508667-B2
Application number	US-201414581825-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method comprising:
providing an integrated circuit (IC) substrate;
depositing a solderable ink on the IC substrate using an ink deposition process, wherein the solderable ink includes a solder powder mixed with a no residue flux (NRF) material that includes a base polymer of polyarylene carbonate (PAC) material and a formic acid fluxing agent; and
reflowing the deposited solderable ink to form one or more solder bumps on the IC substrate, wherein a first solder bump of the one or more solder bumps has a size that is different than a size of a second solder bump of the one or more solder bumps.

2. The method of claim 1 , wherein the solderable ink includes a solder powder mixed with a stabilizing binder that is stable at room temperature and configured to decompose at an elevated temperature above the room temperature.

3. The method of claim 1 , wherein:
the IC substrate includes a contact;
providing the IC substrate comprises providing a die, wafer, or package substrate; and
depositing the solderable ink comprises depositing a solderable material on the contact using an ink jet printer according to a computer-aided design (CAD) file.

4. The method of claim 1 , wherein:
the IC substrate includes a contact;
providing the IC substrate comprises providing a die, wafer, or package substrate; and
depositing the solderable ink comprises depositing a solderable material on the contact using an aerosol jet printing system according to a computer-aided design (CAD) file.

Assignees

• Intel Corp

Inventors

• Prack Edward R

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title