Semiconductor device and a method increasing a resistance value of an electric fuse

Patent metadata

Field	Value
Publication number	US-9508641-B2
Application number	US-201514590294-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Mar 7, 2006
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

First claim

What is claimed is:

1. A semiconductor device, comprising: a semiconductor substrate;
a transistor formed on a main surface of the semiconductor substrate; a first insulator layer formed over the transistor; a first trench formed in the first insulator layer;
a first wiring comprised of a first metal and formed in the first trench,
a second insulator layer formed over the first wiring;
a second trench formed in the second insulator layer;
a second wiring formed in the second trench,
an electric fuse formed of the same layer as that of the first wiring;
a third insulator layer formed over the second insulator layer;
a third wiring formed over the third insulator layer, and
a metal cap film formed to cover an entire upper surface of the first wiring, including an entire upper surface of the electric fuse, the metal cap film being comprised of a metal having a higher electric resistance than the first metal,
wherein a first thickness of the first wiring and the electric fuse is thinner than a second thickness of the second wiring, and
wherein a dielectric relative constant of each of the first insulator layer and the second insulator layer is 3 or less.

2. The semiconductor device according to the claim 1 , wherein the electric fuse is configured so that, when the current exceeding a predetermined level is applied to the electric fuse, the electric fuse is cut.

3. The semiconductor device according to the claim 1 , further comprising a fourth insulator film formed on the electric fuse, wherein an upper surface of the electric fuse is covered with the fourth insulator film.

4. The semiconductor device according to claim 1 , wherein a third thickness of the third wiring is greater than either of the first thickness and the second thickness.

5. The semiconductor device according to claim 4 , wherein a third width of the third wiring is greater than either of a first width of the first wiring and second width of the second wiring.

6. The semiconductor device according to claim 1 , wherein the first metal comprises copper.

7. The semiconductor device according to claim 6 , wherein the second wiring is comprised of copper.

8. The semiconductor device according to claim 6 , wherein the metal cap film is comprised of aluminum.

9. The semiconductor device according to claim 7 , wherein the metal cap film is comprised of aluminum.

Assignees

• Renesas Electronics Corp

Inventors

• Iwamoto Takeshi
• Kono Kazushi
• Arakawa Masashi
• Yonezu Toshiaki
• Obayashi Shigeki

Classifications

• H10W42/80 Primary

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title