High performance power transistor having ultra-thin package

US9508633B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9508633-B2
Application numberUS-201113214801-A
CountryUS
Kind codeB2
Filing dateAug 22, 2011
Priority dateAug 22, 2011
Publication dateNov 29, 2016
Grant dateNov 29, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A field-effect transistor package includes a leadframe with a first linear thickness ( 150 a ) and a leadframe pad ( 151 ) of a reduced thickness; a first terminal of a field-effect transistor chip ( 140 ) attached to the pad and a second and a third terminal remote from the pad; a metal sheet ( 110 ) of a second linear thickness ( 110 a ) connecting the second transistor terminal to a package terminal; a metal sheet ( 112 ) of a third linear thickness ( 112 a ) connecting the third transistor terminal to a package terminal; the sum of the first linear thickness (about 0.125 mm) and the second linear thickness (about 0.125 mm) plus attach material (about 0.05 mm) comprising the package thickness (about 0.3 mm).

First claim

Opening claim text (preview).

We claim: 1. A transistor package comprising: a leadframe of a first linear thickness, the leadframe having a pad; a transistor chip attached to the pad, the transistor having a first terminal in contact with the pad and a second and a third terminal remote from the pad, wherein the leadframe pad has been half-etched to create a cavity into which the transistor chip can be immersed; and a metal sheet of a second linear thickness connecting the second transistor terminal to a p…

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What does patent US9508633B2 cover?
A field-effect transistor package includes a leadframe with a first linear thickness ( 150 a ) and a leadframe pad ( 151 ) of a reduced thickness; a first terminal of a field-effect transistor chip ( 140 ) attached to the pad and a second and a third terminal remote from the pad; a metal sheet ( 110 ) of a second linear thickness ( 110 a ) connecting the second transistor terminal to a pack…
Who is the assignee on this patent?
Herbsommer Juan A, Lopez Osvaldo J, Noquil Jonathan A, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).