Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9508628-B2
Application number	US-201414154329-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Oct 16, 2008
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

First claim

We claim:

1. A semiconductor assembly, comprising:
a semiconductor substrate including a substrate material having a first major surface, a second major surface, and an opening extending from the first major surface to the second major surface, the opening including a generally cylindrical portion extending generally normal to the first major surface and a terminal portion extending transverse to the cylindrical portion and intersecting the second major surface, the terminal portion having a width generally parallel to the plane of the first major surface that is greater than a corresponding width of the cylindrical portion;
a homogeneous volume of conductive material disposed in both the cylindrical portion and the terminal portion of the opening, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a conductive terminal in the terminal portion,
wherein the conductive terminal has a cross-section with generally flat walls, the cross-section being taken in a plane normal to the second major surface,
wherein the conductive terminal projects outwardly away from the second major surface and includes an exposed outwardly facing surface configured for connection to an adjacent structure, and
wherein the conductive terminal has a first cross-sectional width in a first plane that generally corresponds to the second major surface of the semiconductor substrate, and a second cross-sectional width in a second plane that is generally parallel to the first plane and positioned beyond an outermost surface of the semiconductor substrate, wherein the second cross-sectional width is at the exposed outwardly facing surface and is greater than the first cross-sectional width;

a seed layer at an outer boundary of the conductive material at the terminal portion; and
a barrier layer at an outer boundary of the seed layer at the terminal portion, wherein the seed layer and the barrier layer project outward beyond the outermost surface of the semiconductor substrate and extend to the second cross-sectional width of the exposed outwardly facing surface, and wherein the conductive terminal comprises the seed layer, the barrier layer, and the conductive material.

2. The semiconductor assembly of claim 1 , further comprising a microelectronic element in the substrate material and electrically coupled to the conductive material.

3. The semiconductor assembly of claim 1 wherein the conductive material is a solderless material.

4. The semiconductor assembly of claim 3 wherein:
an outer boundary of the conductive terminal tapers laterally outwardly in a direction away from the second major surface; and
the assembly further comprises a solder ball attached to the conductive material at the terminal portion, the solder ball being at least partially aligned along the tapered outer boundary of the conductive terminal.

5. The semiconductor assembly of claim 1 wherein the generally flat walls of the conductive terminal are aligned with crystal planes of the semiconductor substrate material.

6. The semiconductor assembly of claim 1 wherein the conductive material comprises at least 90% copper.

7. The semiconductor assembly of claim 1 wherein the semiconductor substrate is a first semiconductor substrate and the conductive terminal is a first conductive terminal, the semiconductor assembly further comprising:
a second semiconductor substrate including a substrate material having a first major surface, a second major surface, and an opening extending from the first major surface to the second major surface, the opening including a generally cylindrical portion extending generally normal to the first major surface, the cylindrical portion having a generally smooth, uniform surface, the opening further including a terminal portion extending transverse to the cylindrical portion and intersecting the second major surface, the terminal portion having a width generally parallel to the plane of the first major surface that is greater than a corresponding width of the cylindrical portion;
a homogeneous volume of conductive material disposed in both the cylindrical portion and the terminal portion of the opening of the second semiconductor substrate, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a second conductive terminal in the terminal portion; and
a bond pad having a first area facing the first semiconductor substrate and a second area facing the second semiconductor substrate,
wherein the first conductive terminal contacts the first area of the first bond pad and the second conductive terminal contacts the second area of the bond pad.

8. The semiconductor assembly of claim 7 , further comprising:
a first microelectronic element in the first semiconductor substrate and electrically coupled to the first conductive terminal; and
a second microelectronic element in the second semiconductor substrate and electrically coupled to the second conductive terminal.

Assignees

• Micron Technology Inc

Inventors

• Kirby Kyle K
• Parekh Kunal R

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title