Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height

Patent metadata

Field	Value
Publication number	US-9508626-B2
Application number	US-76660710-A
Country	US
Kind code	B2
Filing date	Apr 23, 2010
Priority date	Apr 23, 2010
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a thermally-conductive frame;
forming an opening through the thermally-conductive frame;
depositing a sacrificial material in the opening of the thermally-conductive frame;
forming an interconnect structure over the thermally-conductive frame, the interconnect structure including an electrical conduction path and thermal conduction path;
mounting a first semiconductor die to the electrical conduction path and thermal conduction path of the interconnect structure;
removing the sacrificial material from the opening of the thermally-conductive frame; and
mounting a second semiconductor die over a surface of the thermally-conductive frame opposite the first semiconductor die, the second semiconductor die being electrically connected to the interconnect structure using a first bump disposed in the opening of the thermally-conductive frame.

2. The method of claim 1 , further including removing a portion of a back surface of the first semiconductor die.

3. The method of claim 1 , further including forming a recess in the surface of the thermally-conductive frame opposite the first semiconductor die.

4. The method of claim 1 , further including depositing an underfill beneath the first semiconductor die.

5. The method of claim 1 , further including depositing an encapsulant over the first semiconductor die.

6. The method of claim 1 , further including forming a shielding layer over the first semiconductor die.

7. The method of claim 1 , further including:
forming a plurality of second bumps over the thermally-conductive frame;
depositing an encapsulant over the first semiconductor die and second bumps; and
removing a portion of the encapsulant to expose the second bumps.

8. The method of claim 1 , further including:
forming the opening prior to forming the interconnect structure; and
removing the sacrificial material prior to mounting the second semiconductor die.

9. The method of claim 1 , wherein a portion of the electrical conduction path and a portion of the thermal conduction path each are vertically aligned between a footprint of the first semiconductor die and the thermally-conductive frame.

10. The method of claim 1 , further including forming a second bump over the first semiconductor die and electrically connected to the interconnect structure.

11. The method of claim 1 , wherein forming the interconnect structure further includes:
forming an insulating layer over the thermally-conductive frame;
forming a conductive layer over and extending through the insulating layer to form the electrical conduction path; and
forming a thermally-conductive via through the insulating layer to the thermally-conductive frame to form the thermal conduction path.

12. A method of making a semiconductor device, comprising:
providing a thermally-conductive frame;
forming an interconnect structure over the thermally-conductive frame, the interconnect structure including an electrical interconnect path and thermal conduction path;
mounting a first semiconductor die to the electrical interconnect path and thermal conduction path of the interconnect structure; and
forming an opening through the thermally-conductive frame.

13. The method of claim 12 , further including mounting a second semiconductor die over a surface of the thermally-conductive frame opposite the first semiconductor die with the second semiconductor die electrically connected to the electrical interconnect path of the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

14. The method of claim 13 , further including:
forming the opening prior to forming the interconnect structure;
depositing a sacrificial material in the opening of the thermally-conductive frame; and
removing the sacrificial material prior to mounting the second semiconductor die.

15. The method of claim 12 , wherein forming the interconnect structure further includes:
forming an insulating layer over the thermally-conductive frame;
forming a conductive layer over and extending through the insulating layer to form the electrical interconnect path; and
forming a thermally-conductive via through the insulating layer to the thermally-conductive frame to form the thermal conduction path.

16. The method of claim 12 , further including:
forming a plurality of bumps over the thermally-conductive frame;
depositing an encapsulant over the first semiconductor die and bumps; and
removing a portion of the encapsulant to expose the bumps.

17. The method of claim 12 , further including forming a shielding layer over the first semiconductor die.

18. The method of claim 12 , further including depositing an underfill material between the first semiconductor die and the interconnect structure.

19. The method of claim 12 , further including forming a bump over the first semiconductor die and electrically connected to the interconnect structure.

20. A semiconductor device, comprising:
a thermally-conductive frame;
an interconnect structure formed over the thermally-conductive frame, the interconnect structure including an electrical interconnect path and thermal conduction path;
a first semiconductor die mounted to the electrical interconnect path and thermal conduction path of the interconnect structure;
an opening formed in the thermally-conductive frame; and
a second semiconductor die mounted over a surface of the thermally-conductive frame opposite the first semiconductor die and electrically connected to the electrical interconnect path of the interconnect structure using a first bump disposed in the opening of the thermally-conductive frame.

21. The semiconductor device of claim 20 , wherein the interconnect structure includes:
an insulating layer formed over the thermally-conductive frame;
a conductive layer formed over and extending through the insulating layer to form the electrical interconnect path; and
a thermally-conductive via formed through the insulating layer to the thermally-conductive frame to form the thermal conduction path.

22. The semiconductor device of claim 20 , wherein a portion of a back surface of the first semiconductor die is removed.

23. The semiconductor device of claim 20 , further including forming a shielding layer over the first semiconductor die.

24. The semiconductor device of claim 20 , further including:
a plurality of second bumps formed over the thermally-conductive frame; and
an encapsulant deposited over the first semiconductor die and second bumps, wherein a portion of the encapsulant is removed to expose the second bumps.

25. The semiconductor device of claim 20 , further including an underfill material deposited between the first semiconductor die and the interconnect structure.

26. The semiconductor device of claim 20 , further including forming a second bump over the first semiconductor die and electrically connected to the interconnect structure.

Assignees

• Pagaila Reza A
• Lin Yaojian
• Stats Chippac Pte Ltd

Inventors

• Pagaila Reza A
• Lin Yaojian

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title