Alignment of three dimensional integrated circuit components

Patent metadata

Field	Value
Publication number	US-9508614-B2
Application number	US-201414573641-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 12, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.

First claim

What is claimed is:

1. A method for aligning a chip onto a substrate comprising:
depositing a ferrofluid, the ferrofluid being a colloidal liquid made of magnetic nanoparticles suspended within a solvent and having a particular surface tension, onto a substrate having one or more pads that electrically couple to a semiconductor layer;
placing a chip with one or more solder balls that electrically couple to logic elements of the chip onto the deposited ferrofluid;
supporting the chip on the ferrofluid, in a substantially coplanar orientation to the substrate;
determining that the one or more solder balls of the chip are misaligned from a desired location on the one or more pads of the substrate; and
adjusting, in response to the determination that the one or more solder balls of the chip are misaligned from the desired location on the one or more pads of the substrate, a position of the ferrofluid within a three-dimensional space with a magnetic field until the one or more solder balls of the chip are aligned in the desired location on the one or more pads of the substrate.

2. The method of claim 1 , wherein the substrate is a wafer.

3. The method of claim 1 , wherein the one or more pads of the substrate further electrically couple to a second chip having one or more through silicon vias that electrically couple to the semiconductor layer.

4. The method of claim 1 , wherein the placing of the chip in the ferrofluid further comprises:
measuring a height of the one or more solder balls;
aligning the chip with the one or more solder balls roughly above the desired location on the one or more pads of the substrate before placement on the ferrofluid;
monitoring a height of the ferrofluid; and
adjusting the height of the ferrofluid in response to the height of the ferrofluid being less than the height of the solder balls.

5. The method of claim 4 , wherein the adjusting the height of the ferrofluid further comprises:
adding a particular volumne of the ferrofluid between the chip and the substrate.

6. The method of claim 4 , wherein the adjusting the height of the ferrofluid further comprises:
adjusting a strength of the magnetic field.

7. The method of claim 6 , wherein the adjusting a strength of the magnetic field further comprises:
manipulating the position of a magnet in a three-dimensional space relative to the ferrofluid.

8. The method of claim 1 , further comprising:
determining that the chip is aligned with the substrate; and
bonding the chip to the substrate in response to the determination that the one or more solder balls of the chip are aligned with the one or more pads of the substrate.

9. The method of claim 8 , wherein bonding the chip to the substrate further comprises:
tacking the chip to the substrate.

10. The method of claim 8 , wherein bonding the chip to the substrate further comprises:
coupling the chip to the substrate electrically.

Assignees

• IBM

Inventors

• Kuczynski Joseph
• Mann Phillip V
• O'Connell Kevin M
• Sinha Arvind K
• Stathakis Karl

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title