Tunneling field effect transistor device and related manufacturing method

Patent metadata

Field	Value
Publication number	US-9508606-B2
Application number	US-201514845466-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Sep 22, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set.

First claim

What is claimed is:

1. A method for manufacturing a transistor device, the method comprising:
forming an InSb layer on a substrate;
forming a GaSb layer on the substrate;
forming a first gate member that partially overlaps the InSb layer, such that a first portion of the InSb layer and a second portion of the InSb layer are not covered by the first gate member;
forming a second gate member that partially overlaps the GaSb layer, such that a first portion of the GaSb layer and a second portion of the GaSb layer are not covered by the second gate member;
doping a first first-type dopant set in the first portion of the InSb layer;
doping a first second-type dopant set in the second portion of the InSb layer;
doping a second first-type dopant set in the second portion of the GaSb layer; and
doping a second second-type dopant set in the first portion of the GaSb layer.

2. The method of claim 1 , further comprising:
forming a first oxide layer on the InSb layer before the forming the first gate member, wherein a dielectric constant of the first oxide layer is greater than or equal to 3.9;
forming the first gate member on the first oxide layer;
forming a second oxide layer on the GaSb layer before the forming the second gate member, wherein a dielectric constant of the second oxide layer is greater than or equal to 3.9; and
forming the second gate member on the second oxide layer.

3. The method of claim 2 , further comprising:
forming a first spacer that covers both a first side of the first gate member and a first side of the first oxide layer;
forming a second spacer that covers both a second side of the first gate member and a second side of the first oxide layer;
forming a third spacer that covers both a first side of the second gate member and a first side of the second oxide layer; and
forming a fourth spacer that covers both a second side of the second gate member and a second side of the second oxide layer.

4. The method of claim 1 , wherein a third portion of the InSb layer is covered by the first gate member and is disposed between the first portion of the InSb layer and the second portion of the InSb layer, and wherein a third portion of the GaSb layer is covered by the second gate member and is disposed between the first portion of the GaSb layer and the second portion of the GaSb layer.

5. The method of claim 1 , wherein at least one of the forming the InSb layer and the forming the GaSb layer includes performing selective epitaxial growth.

6. The method of claim 1 , wherein the substrate includes a silicon base substrate, a Ge layer, and a SiGe layer positioned between the silicon base substrate and the Ge layer.

7. The method of claim 1 , wherein each of the first first-type dopant set and the second first-type dopant set includes an n-type dopant, and wherein each of the first second-type dopant set and the second second-type dopant set includes a p-type dopant.

8. The method of claim 1 , wherein each of the first first-type dopant set and the second first-type dopant set includes a p-type dopant, and wherein each of the first second-type dopant set and the second second-type dopant set includes an n-type dopant.

9. The method of claim 1 , wherein a dopant concentration of each of the first first-type dopant set in the first portion of the InSb layer, the first second-type dopant set in the second portion of the InSb layer, the second first-type dopant set in the second portion of the GaSb layer, and the second second-type dopant set in the first portion of the GaSb layer is at least 1×10 19 cm −3 .

10. The method of claim 1 , wherein the first portion of the InSb layer forms a source portion of an n-type tunneling field effect transistor, and wherein the second portion of the GaSb layer forms a drain portion of a p-type tunneling field effect transistor.

11. The method of claim 1 , wherein the first portion of the InSb layer and the second portion of the GaSb layer are positioned between the second portion of the InSb layer and the first portion of the GaSb layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xiao Deyuan

Classifications

• H10P14/3222

  Antimonides · CPC title

• H10P14/3422

  Antimonides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title