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US-2024395343-A1 · Nov 28, 2024 · US
Program and read trim setting
US9508440B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9508440-B2 |
| Application number | US-201514688149-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 16, 2015 |
| Priority date | Sep 1, 2005 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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Abstract
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A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of increasing program reliability in a NAND memory, comprising: identifying a plurality of portions of the NAND memory; testing a plurality of trim settings stored in a trim setting register to determine which trim setting of the plurality of trim settings is best for a respective portion of the plurality of portions of the NAND memory; and assigning the determined best trim setting to the respective portion of the plurality of portions of the N…
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- G11C16/10Primary
Physics · mapped topic
Physics · mapped topic
- G11C16/102Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9508440B2 cover?
- A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).