Array structure of single-ploy nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9508396-B2
Application number	US-201414471613-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Apr 2, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

First claim

What is claimed is:

1. An array structure of a single-poly nonvolatile memory, the array structure comprising:
a first word line;
a second word line;
a first source line;
a second source line, wherein the second source line and the first source line are different;
a first erase line;
a first bit line;
a first memory cell comprising a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the first source line, a gate terminal of the first PMOS transistor is connected to the first word line, a drain terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor, a drain terminal of the second PMOS transistor is connected to the first bit line, a gate terminal of the second PMOS transistor is connected to a gate terminal of the first NMOS transistor, and a drain terminal and a source terminal of the first NMOS transistor are connected to the first erase line; and
a second memory cell comprising a third PMOS transistor, a fourth PMOS transistor and a second NMOS transistor, wherein a source terminal of the third PMOS transistor is connected to the second source line, a gate terminal of the third PMOS transistor is connected to the second word line, a drain terminal of the third PMOS transistor is connected to a source terminal of the fourth PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the first bit line, a gate terminal of the fourth PMOS transistor is connected to a gate terminal of the second NMOS transistor, and a drain terminal and a source terminal of the second NMOS transistor are connected to the first erase line,
wherein the gate terminal of the second PMOS transistor and the gate terminal of the first NMOS transistor are connected to a first floating gate, and the gate terminal of the fourth PMOS transistor and the gate terminal of the second NMOS transistor are connected to a second floating gate.

2. The array structure as claimed in claim 1 , further comprising:
a second bit line;
a third memory cell comprising a fifth PMOS transistor, a sixth PMOS transistor and a third NMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the first source line, a gate terminal of the fifth PMOS transistor is connected to the first word line, a drain terminal of the fifth PMOS transistor is connected to a source terminal of the sixth PMOS transistor, a drain terminal of the sixth PMOS transistor is connected to the second bit line, a gate terminal of the sixth PMOS transistor is connected to a gate terminal of the third NMOS transistor, and a drain terminal and a source terminal of the third NMOS transistor are connected to the first erase line; and
a fourth memory cell comprising a seventh PMOS transistor, an eighth PMOS transistor and a fourth NMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to the second source line, a gate terminal of the seventh PMOS transistor is connected to the second word line, a drain terminal of the seventh PMOS transistor is connected to a source terminal of the eighth PMOS transistor, a drain terminal of the eighth PMOS transistor is connected to the second bit line, a gate terminal of the eighth PMOS transistor is connected to a gate terminal of the fourth NMOS transistor, and a drain terminal and a source terminal of the fourth NMOS transistor are connected to the first erase line,
wherein the gate terminal of the sixth PMOS transistor and the gate terminal of the third NMOS transistor are connected to a third floating gate, and the gate terminal of the eighth PMOS transistor and the gate terminal of the fourth NMOS transistor are connected to a fourth floating gate.

3. The array structure as claimed in claim 1 , further comprising:
a third word line;
a second erase line, wherein the second erase line and the first erase line are different;
a fifth memory cell comprising a ninth PMOS transistor, a tenth PMOS transistor and a fifth NMOS transistor, wherein a source terminal of the ninth PMOS transistor is connected to the second source line, a gate terminal of the ninth PMOS transistor is connected to the third word line, a drain terminal of the ninth PMOS transistor is connected to a source terminal of the tenth PMOS transistor, a drain terminal of the tenth PMOS transistor is connected to the first bit line, a gate terminal of the tenth PMOS transistor is connected to a gate terminal of the fifth NMOS transistor, and a drain terminal and a source terminal of the fifth NMOS transistor are connected to the second erase line,
wherein the gate terminal of the tenth PMOS transistor and the gate terminal of the fifth NMOS transistor are connected to a fifth floating gate.

4. The array structure as claimed in claim 3 , further comprising:
a fourth word line;
a third source line, wherein the third source line and the second source line and the first source line are different;
a sixth memory cell comprising a eleventh PMOS transistor, a twelfth PMOS transistor and a sixth NMOS transistor, wherein a source terminal of the eleventh PMOS transistor is connected to the third source line, a gate terminal of the eleventh PMOS transistor is connected to the fourth word line, a drain terminal of the eleventh PMOS transistor is connected to a source terminal of the twelfth PMOS transistor, a drain terminal of the twelfth PMOS transistor is connected to the first bit line, a gate terminal of the twelfth PMOS transistor is connected to a gate terminal of the sixth NMOS transistor, and a drain terminal and a source terminal of the sixth NMOS transistor are connected to the second erase line,
wherein the gate terminal of the twelfth PMOS transistor and the gate terminal of the sixth NMOS transistor are connected to a sixth floating gate.

Assignees

• Ememory Technology Inc

Inventors

• Chen Wei-Ren
• Lee Wen-Hao

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title