Method of driving display device including comparator circuit, and display device including comparator circuit

Patent metadata

Field	Value
Publication number	US-9508276-B2
Application number	US-201313920433-A
Country	US
Kind code	B2
Filing date	Jun 18, 2013
Priority date	Jun 29, 2012
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

In a second memory device, (n+1)th frame image data in an mth row (m is a natural number) is stored. In a comparator circuit, the nth frame image data in the mth row and the (n+1)th frame image data in the mth row are compared and determination data is output to a writing control circuit. In the writing control circuit, writing using the (n+1)th frame image data to a pixel in the mth row is not performed when the determination data indicates sameness, or the writing using the (n+1)th frame image data to the pixel in the mth row is performed when the determination data indicates difference. When performed in two or more successive frame periods, the writing using the (n+1)th frame image data is performed while video voltages having the same polarity are applied.

First claim

What is claimed is:

1. A display device comprising:
a pixel portion including a plurality of gate lines arranged in a plurality of rows;
a first memory device which is a frame memory, the frame memory being capable of storing an nth frame image data (n is a natural number);
a second memory device which is a line memory, the line memory being capable of storing an (n+1)th frame image data in an mth row (m is a natural number);
a comparator circuit configured to compare the nth frame image data and the (n+1)th frame image data row by row, and generate a plurality of determination data each corresponding to one of the plurality of rows; and
a writing control circuit configured to control a selection of the plurality of gate lines row by row in each frame period, based on the plurality of determination data supplied from the comparator circuit,
wherein each of the plurality of determination data indicates whether the nth frame image data in one of the plurality of rows and the (n+1)th frame image data in a corresponding row are the same or different,
wherein, when one of the plurality of determination data indicates that a first data which is the nth frame image data in the mth row and a second data which is the (n+1)th frame image data in the mth row are the same, the writing control circuit does not select the gate line in the mth row,
wherein, when the one of the plurality of determination data indicates that the first data and the second data are different, the writing control circuit selects the gate line in the mth row,
wherein the second memory device supplies the (n+1)th frame image data in the mth row to the first memory device so that the nth frame image data in the mth row is overwritten with the (n+1)th frame image data in the mth row in the first memory device, and
wherein a number of the plurality of rows is the same as a number of the plurality of determination data which are generated by comparing the nth frame image data and the (n+1)th frame image data.

2. The display device according to claim 1 ,
wherein the display device further comprises a driver circuit electrically connected to the pixel portion,
wherein, when one of the plurality of determination data indicates that the first data and the second data are the same, the writing control circuit controls the driver circuit so that the second data is not written to the pixel portion, and
wherein, when the one of the plurality of determination data indicates that the first data and the second data are different, the writing control circuit controls the driver circuit so that the second data is written to the pixel portion.

3. The display device according to claim 1 , wherein, when the gate line in the mth row is selected in two or more successive frame periods, video voltages having same polarity are input to the pixel portion in the two or more successive frame periods.

4. The display device according to claim 1 ,
wherein the pixel portion comprises a plurality of pixels arranged in the plurality of rows,
wherein each of the plurality of pixels comprises a transistor and a liquid crystal element, and
wherein a channel formation region of the transistor comprises an oxide semiconductor.

5. The display device according to claim 1 ,
wherein the pixel portion comprises a plurality of pixels arranged in the plurality of rows,
wherein each of the plurality of pixels comprises a transistor and a liquid crystal element,
wherein a channel formation region of the transistor comprises an oxide semiconductor, and
wherein an off-state current per micrometer of a channel width of the transistor is less than or equal to 10 zA.

6. The display device according to claim 1 ,
wherein the pixel portion comprises a plurality of pixels arranged in the plurality of rows,
wherein each of the plurality of pixels comprises a transistor and a liquid crystal element,
wherein a channel formation region of the transistor comprises an oxide semiconductor, and
wherein an off-state current per micrometer of a channel width of the transistor is less than or equal to 10 zA at room temperature when a voltage between a source and a drain of the transistor is 10 V.

7. The display device according to claim 1 ,
wherein the pixel portion comprises a plurality of pixels arranged in the plurality of rows,
wherein each of the plurality of pixels comprises a first transistor, a second transistor, and a liquid crystal element,
wherein a gate of the first transistor is electrically connected to one of the plurality of gate lines, and
wherein a gate of the second transistor is electrically connected to a selection line.

8. The display device according to claim 1 , wherein the comparator circuit comprises a first logic circuit and a second logic circuit which are electrically connected in series.

9. A driving method of a display device, the display device comprising:
a pixel portion including a plurality of gate lines arranged in a plurality of rows;
a first memory device which is a frame memory, the frame memory being capable of storing an nth frame image data (n is a natural number);
a second memory device which is a line memory, the line memory being capable of storing an (n+1)th frame image data in an mth row (m is a natural number);
a comparator circuit; and
a writing control circuit,
the driving method comprising steps of:
storing the nth frame image data (n is a natural number) in the first memory device;
storing the (n+1)th frame image data in the mth row (m is a natural number) in the second memory device;
comparing the nth frame image data and the (n+1)th frame image data row by row in the comparator circuit;
generating a plurality of determination data each corresponding to one of the plurality of rows in the comparator circuit; and
supplying the plurality of determination data from the comparator circuit to the writing control circuit,
wherein the writing control circuit controls a selection of the plurality of gate lines row by row in each frame period, based on the plurality of determination data,
wherein each of the plurality of determination data indicates whether the nth frame image data in one of the plurality of rows and the (n+1)th frame image data in a corresponding row are the same or different,
wherein, when one of the plurality of determination data indicates that a first data which is the nth frame image data in the mth row and a second data which is the (n+1)th frame image data in the mth row are the same, the writing control circuit does not select the gate line in the mth row,
wherein, when the one of the plurality of determination data indicates that the first data and the second data are different, the writing control circuit selects the gate line in the mth row, and
wherein the second memory device supplies the (n+1)th frame image data in the mth row to the first memory device so that the nth frame image data in the mth row is overwritten with the (n+1)th frame image data in the mth row in the first memory device.

10. The driving method of a display device according to claim 9 , wherein, when the gate line in the mth row is selected in two or more successive frame periods, video voltages having same polarity are input to the pixel portion in the two or more successive frame periods.

11. The driving method of a display device according to claim 9 ,
wherein the display device further comprises a driver circuit electrically connected to the pixel portion,
wherein, when one of the plurality of determination data indicates that the first data and the second data are the same, the writing control circuit controls the driver circuit so that the second data is not written to the pixel portion,

Assignees

• Semiconductor Energy Lab

Inventors

• Hirakata Yoshiharu
• Yamazaki Shunpei

Classifications

• G09G2310/04

  Partial updating of the display screen · CPC title

• G09G2360/12

  Frame memory handling · CPC title

• G09G2330/02

  Details of power systems and of start or stop of display operation · CPC title

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title