Method and apparatus for secure execution using a secure memory partition

Patent metadata

Field	Value
Publication number	US-9507962-B2
Application number	US-201414583054-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Jun 30, 2000
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

First claim

I claim:

1. A processor comprising:
a plurality of general purpose registers;
cryptographic logic to encrypt and decrypt information, the cryptographic logic to support a Data Encryption Standard (DES) algorithm, a triple DES (3DES) algorithm, a Rivest-Shamir-Adleman (RSA) algorithm, and a Diffie Hellman algorithm;
an on-die read only memory to store bootstrap security logic to copy code from a non-volatile memory device to a dynamic random access memory and to verify an authe…

Assignees

• Intel Corp

Inventors

• Mittal Millind

Classifications

• G06F21/602

  Physics · mapped topic

• G06F2221/2107

  Physics · mapped topic

• G06F12/1408

  Physics · mapped topic

• G06F12/1491

  Physics · mapped topic

• G06F21/72 Primary

  Physics · mapped topic