Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
US9507895B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507895-B2 |
| Application number | US-201113702636-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 13, 2011 |
| Priority date | Jun 8, 2010 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
Opening claim text (preview).
The invention claimed is: 1. A simulation apparatus comprising: a discrete events simulation processor configured to perform a discrete type simulation of a configured model comprising a plurality of different components based on attribute information associated with each of the plurality of different components of the configured model and based on connection information showing a connectional relationship among the plurality of different components of the configured model; a so…
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