Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
US-2024319762-A1 · Sep 26, 2024 · US
Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
US9507883B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507883-B2 |
| Application number | US-201313925764-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 24, 2013 |
| Priority date | Jun 24, 2013 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for designing a system on a target device: mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system; and generating a visual representation of the mapping. 2. The method of claim 1 , wherein the mapping of the high-level description accounts for wire use of the system and wire resources on the target device. 3. T…
Assignees
Inventors
Classifications
- G06F30/34Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9507883B2 cover?
- A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
- Who is the assignee on this patent?
- Altera Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F30/34. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).