Method and processor for reducing code and latency of TLB maintenance operations in a configurable processor

Patent metadata

Field	Value
Publication number	US-9507729-B2
Application number	US-201414503152-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Oct 1, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

First claim

What is claimed is:

1. A memory management unit (MMU) for storing mappings between virtual addresses and physical addresses, the MMU comprising:
a translation look-aside buffer (TLB) configured to store mappings between virtual address and physical address; and
a memory management unit (MMU) controller configured to:
receive a request to insert an entry into the TLB, the request comprising a virtual address and a physical address, and
responsive to receiving the request to in…

Assignees

• Synopsys Inc

Inventors

• Popat Kaushik L
• Gupta Vineet
• Kite Martin

Classifications

• G06F12/1036

  Physics · mapped topic

• G06F12/1027 Primary

  Physics · mapped topic