GPU shared virtual memory working set management

Patent metadata

Field	Value
Publication number	US-9507726-B2
Application number	US-201414262475-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Apr 25, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.

First claim

What is claimed is:

1. A non-transitory machine-readable medium having executable instructions to cause one or more processing units to perform a method to track virtual memory access by a graphics processing unit of a device, the method comprising:
detecting a virtual memory access to a virtual memory address by a processing unit, wherein the device includes a central processing unit and the graphics processing unit that are each able to access the virtual memory address;
determining if the processing unit is a graphic processing unit; and
if the processing unit is the graphics processing unit, setting a graphics processing unit reference bit in a page table entry of a page table that corresponds to the virtual memory address, wherein the graphics processing unit reference bit indicates whether the graphics processing unit has recently accessed the virtual memory address, the page table entry further includes a central processing unit reference bit that indicates whether the central processing unit has recently accessed the virtual memory address, and the page table is shared between the central processing unit and the graphic processing unit.

2. The non-transitory machine-readable medium of claim 1 , further comprising:
locating the page table entry.

3. The non-transitory machine-readable medium of claim 1 , wherein if there is not a page table entry that corresponds to the virtual memory address,
creating the page table entry.

4. The non-transitory machine-readable medium of claim 1 , wherein the page table entry includes a physical address that is mapped to the virtual machine address.

5. The non-transitory machine-readable medium of claim 1 , wherein the virtual machine access is selected from the group consisting of a read access to the virtual memory address and a write access to the virtual memory address.

6. A method to track virtual memory access by a graphics processing unit of a device, the method comprising:
detecting an access to a virtual memory address by a processing unit, wherein the device includes a central processing unit and the graphics processing unit that are each able to access the virtual memory address;
determining if the processing unit is a graphic processing unit; and
if the processing unit is the graphics processing unit,
setting a graphics processing unit reference bit in a page table entry of a page table that corresponds to the virtual memory address, wherein the graphics processing unit reference bit indicates whether the graphics processing unit has recently accessed the virtual memory address, the page table entry further includes a central processing unit reference bit that indicates whether the central processing unit has recently accessed the virtual memory address, and the page table is shared between the central processing unit and the graphic processing unit.

7. The method of claim 6 , further comprising:
locating the page table entry.

8. The method of claim 7 , wherein if there is not a page table entry that corresponds to the virtual memory address,
creating the page table entry.

9. The method of claim 6 , wherein the page table entry includes a physical address that is mapped to the virtual machine address.

10. The method of claim 6 , wherein the virtual machine access is selected from the group consisting of a read access to the virtual memory address and a write access to the virtual memory address.

11. A device that tracks virtual memory access by a graphics processing unit of the device, the device comprising:
a processor;
a memory coupled to the processor though a bus; and
a process executed from the memory by the processor that causes the processor to detect an access to a virtual memory address by a processing unit, wherein the device includes a central processing unit and the graphics processing unit that are each able to access the virtual memory address, determine if the processing unit is a graphic processing unit, and if the processing unit is the graphics processing unit, set a graphics processing unit reference bit in a page table entry of a page table that corresponds to the virtual memory address, wherein the graphics processing unit reference bit indicates whether the graphics processing unit has recently accessed the virtual memory address, the page table entry further includes a central processing unit reference bit that indicates whether the central processing unit has recently accessed the virtual memory address, and the page table is shared between the central processing unit and the graphic processing unit.

12. The device of claim 11 , wherein the processor further causes the processor to locate the page table entry.

13. The device of claim 11 , wherein if there is not a page table entry that corresponds to the virtual memory address, the processor further causes the processor to create the page table entry.

14. The device of claim 11 , wherein the page table entry includes a central processing unit reference bit.

15. The device of claim 11 , wherein the page table entry includes a physical address that is mapped to the virtual machine address.

Assignees

• Apple Inc

Inventors

• Kumar Derek R

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1072

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title