Methods, systems, and computer readable media for solid state drive caching across a host bus

Patent metadata

Field	Value
Publication number	US-9507722-B2
Application number	US-201414297563-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 5, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface.

First claim

What is claimed is:

1. A method for solid state caching across host bus, the method comprising:
during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bus interface located on the SSD for accessing a second RAM located on a host and separate from the first RAM:
using the first RAM as a cache for storing a first portion of metadata; and
using the second RAM as a cache for storing a second portion of metadata, wherein the second RAM is accessed by the SSD via the host bus interface located on the SSD using a protocol that allows the SSD to be the master of the host bus and directly read from and write to memory space of the cache implemented using the second RAM, wherein the host is configured to notify the SDD of an intent to reclaim at least a portion of the memory space in the second RAM that is allocated to the SSD and transfer some or all of the second portion of metadata back to the SSD via the host bus or provide the SDD an opportunity to request and retrieve some or all of the second portion of metadata.

2. The method of claim 1 wherein metadata comprises at least one of:
control tables for management of the NVM on the SSD;
configuration data for the SSD;
garbage collection data for sources available on the SSD; and
data used by a flash translation layer (FTL).

3. The method of claim 1 wherein using the first RAM as a cache for storing a first portion of metadata and using the second RAM as a cache for storing a second portion of metadata includes:
receiving an I/O request from the host;
in response to receiving an I/O request from the host, determining whether first metadata associated with the I/O request is stored in the first RAM;
in response to determining that first metadata is stored in the first RAM, retrieving the first metadata from the first RAM and using the retrieved metadata to process the I/O request;
in response to determining that the first metadata is not stored in the first RAM, determining whether the first metadata is stored in the second RAM;
in response to determining that the first metadata is stored in the second RAM, retrieving the first metadata from the second RAM via the host bus and using the retrieved metadata to process the I/O request; and
in response to determining that the first metadata is not stored in the second RAM, retrieving the first metadata from the NVM and using the retrieved metadata to process the I/O request.

4. The method of claim 1 comprising, after retrieving the first metadata, determining whether to store at least some metadata in the second RAM, and, upon a determination that some metadata should be stored in the second RAM, identifying metadata to be stored in the second RAM and transferring the identified metadata into the second RAM via the host bus.

5. The method of claim 1 wherein the host bus interface comprises a non-volatile memory express (NVMe) interface.

6. The method of claim 5 wherein using the second RAM as a cache includes reserving a portion of the second RAM by issuing requests for host address buffer space.

7. The method of claim 2 wherein the second portion of metadata comprises metadata that can be recreated by the SSD in the event that the SSD loses access to the second RAM.

8. The method of claim 1 wherein the host bus interface comprises a peripheral component interconnect express (PCIe) interface and wherein the method further comprises utilizing a high priority virtual channel accessible via the PCIe interface for transferring metadata to and from the second RAM memory and a low priority virtual channel for transferring data to and from the second RAM memory.

9. The method of claim 1 wherein the NVM comprises a 3D NAND NVM.

10. A system for solid state caching across host bus, the system comprising:
a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bus interface located on the SSD for accessing a second RAM memory located on a host and separate from the first RAM, wherein the SSD drive is configured to:
use the first RAM as a cache for storing a first portion of metadata; and
use the second RAM as a cache for storing a second portion of metadata, wherein the second RAM is accessed by the SSD via the host bus interface located on the SSD using a protocol that allows the SSD to be the master of the host bus and directly read from and write to memory space of the cache implemented using the second RAM, wherein the host is configured to notify the SDD of an intent to reclaim at least a portion of the memory space in the second RAM that is allocated to the SSD and transfer some or all of the second portion of metadata back to the SSD via the host bus or provide the SDD an opportunity to request and retrieve some or all of the second portion of metadata.

11. The system of claim 10 wherein metadata comprises at least one of:
control tables for management of the NVM on the SSD;
configuration data for the SSD;
garbage collection data for sources available on the SSD; and
data used by a flash translation layer (FTL).

12. The system of claim 10 wherein the SSD is configured for:
receiving an I/O request from the host;
in response to receiving an I/O request from the host, determining whether first metadata associated with the I/O request is stored in the first RAM;
in response to determining that first metadata is stored in the first RAM, retrieving the first metadata from the first RAM and using the retrieved metadata to process the I/O request;
in response to determining that the first metadata is not stored in the first RAM, determining whether the first metadata is stored in the second RAM;
in response to determining that the first metadata is stored in the second RAM, retrieving the first metadata from the second RAM via the host bus and using the retrieved metadata to process the I/O request; and
in response to determining that the first metadata is not stored in the second RAM, retrieving the first metadata from the NVM and using the retrieved metadata to process the I/O request.

13. The system of claim 10 wherein the SSD is configured for, after retrieving the first metadata, determining whether to store at least some metadata in the second RAM, and, upon a determination that some metadata should be stored in the second RAM, identifying metadata to be stored in the second RAM and transferring the identified metadata into the second RAM via the host bus.

14. The system of claim 10 wherein the host bus interface comprises a non-volatile memory express (NVMe) interface.

15. The system of claim 14 wherein using the second RAM as a cache includes reserving a portion of the second RAM by issuing requests for host address buffer space.

16. The system of claim 10 wherein the second portion of metadata comprises metadata that can be recreated by the SSD in the event that the SSD loses access to the second RAM.

17. The system of claim 10 wherein the host bus interface comprises a peripheral component interconnect express (PCIe) interface and wherein the host bus interface utilizes a high priority virtual channel accessible via the PCIe interface for transferring metadata to and from the second RAM memory and a low priority virtual channel for transferring data to and from the second RAM memory.

18. The system of claim 10 wherein the NVM comprises a 3D NAND NVM.

19. A non-transitory computer readable medium having stored

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Desai Girish Bhaurao
• Dhulipala Venkata Krishna Nadh

Classifications

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0868 Primary

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/311

  In host system · CPC title