Coherence-based attack detection
US-12147528-B2 · Nov 19, 2024 · US
Coherency probe with link or domain indicator
US9507715B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507715-B2 |
| Application number | US-201414523045-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2014 |
| Priority date | Oct 24, 2014 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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Abstract
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A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: identifying a first coherency probe as a multicast probe based on a coherency state of a memory address corresponding to the first coherency probe; in response to receiving the first coherency probe at a processing module of a processor and in response to identifying that the first coherency probe is a multicast probe: identifying a subset of a plurality of processing modules of the processor based on a field of the coherency probe, t…
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- G06F12/0815Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
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Frequently asked questions
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- What does patent US9507715B2 cover?
- A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that…
- Who is the assignee on this patent?
- Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0815. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).