Nonvolatile memory device and data storage device including the same

Patent metadata

Field	Value
Publication number	US-9507707-B2
Application number	US-201414200349-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Dec 19, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A data storage device including a first nonvolatile memory device having a first state information transmission block, a second nonvolatile memory device having a second state information transmission block, which shares a state information line with the first state information transmission block, and a controller having a state information reception block which is suitable for transmitting a control signal for controlling the first state information transmission block and the second state information transmission block to transmit a state information frame, and sequentially receiving a first state information frame transmitted from the first state information transmission block and a second state information frame transmitted from the second state information transmission block, through the state information line.

First claim

What is claimed is:

1. A data storage device comprising:
a first nonvolatile memory device including a first state information transmission block;
a second nonvolatile memory device including a second state information transmission block, which shares a state information line with the first state information transmission block; and
a controller including a state information reception block suitable for transmitting a control signal for controlling the first state information transmission block and the second state information transmission block to transmit a state information frame, and sequentially receiving a first state information frame transmitted from the first state information transmission block and a second state information frame transmitted from the second state information transmission block through the state information line,
wherein the first state information transmission block determines whether to transmit the first state information frame based on a first transmission ID and a number of transmissions of all the state information frames transmitted through the state information line,
wherein the second state information transmission block determines whether to transmit the second state information frame based on a second transmission ID and the number of transmissions, and
wherein the first transmission ID represents a transmission order of the first state information transmission block is set by the controller and the second transmission ID represents a transmission order of the second state information transmission block is set by the controller.

2. The data storage device according to claim 1 , wherein the first state information transmission block transmits the first state information frame when the number of transmissions is equal to a value of the first transmission ID minus 1, and stands by transmission of the first state information frame when the number of transmission is different from the value of the first transmission ID minus 1.

3. The data storage device according to claim 1 , wherein the second state information transmission block transmits the second state information frame when the number of transmissions is equal to a value of the second transmission ID minus 1, and stands by transmission of the second state information frame when the number of transmissions is different from the value of the second transmission ID minus 1.

4. The data storage device according to claim 1 , wherein the first and second state information frames include first and second state information representing operation states of the first and second nonvolatile memory devices, respectively, and
wherein the first state information transmission block generates the first state information frame by adding, to the first state information, error detection information of the first state information, and
wherein the second state information transmission block generates the second state information frame by adding, to the second state information, error detection information of the second state information.

5. The data storage device according to claim 4 , wherein the first state information transmission block generates the first state information frame including only transmission start information and transmission end information when the first state information is not changed, and
wherein the second state information transmission block generates the second state information frame including only transmission start information and transmission end information when the second state information is not changed.

6. The data storage device according to claim 1 , wherein the state information reception block comprises:
an input/output block suitable for performing a control task to enable bidirectional communication through the state information line;
an error information decoding block suitable for detecting an error of first and second state information of the first and second nonvolatile memory devices included in the first and second state information frames based on error detection information included in the first and second state information frames, respectively;
a reception management block suitable for generating the control signal, and extracting the state information from the received first and second state information frames; and
a state information storage block suitable for storing the extracted state information according to control of the reception management block.

7. The data storage device according to claim 6 , wherein the input/output block comprises a tri-state buffer suitable for operating in an open state or a closed state according to control of the reception management block, and
wherein the tri-state buffer transmits the control signal provided from the reception management block to the state information line in the open state, and blocks output of the control signal to the state information line in the closed state.

8. The data storage device according to claim 6 , wherein the reception management block regenerates the control signal when it is informed that an error in the first or second state information has been detected by the error information decoding block.

9. A nonvolatile memory device comprising: a memory cell array;
a control logic suitable for controlling an operation such that data is stored in the memory cell array or data is read from the memory cell array; and
a state information transmission block suitable for generating a state information frame based on state information provided by the control logic, and sequentially transmitting the state information frame through a state information line to an exterior device,
wherein the state information transmission block determines whether to transmit the state information frame based on a transmission ID and a number of transmissions of all the state information frames transmitted through the state information line, and
wherein the transmission ID represents a transmission order of the state information transmission block-set by a controller.

10. The nonvolatile memory device according to claim 9 , wherein, when a control signal for controlling transmission of the state information frame is transmitted through the state information line from the exterior device, the state information transmission block transmits the state information frame in response to the control signal.

11. The nonvolatile memory device according to claim 9 , wherein the state information transmission block generates the state information frame by adding transmission start information, error detection information about the state information, and transmission end information in addition to the state information.

12. The nonvolatile memory device according to claim 11 , wherein the state information transmission block generates the state information frame without the state information and the error detection information when the state information is not changed.

13. The nonvolatile memory device according to claim 9 , wherein the control logic provides the state information, which indicates that an operation for the memory cell array is in progress, or on standby, and a pass or a fail, to the state information transmission block.

14. The nonvolatile memory device according to claim 9 , wherein the state information transmission block comprises: an input/output block suitable for performing a control task to enable bidirectional communication through the state information line;
an error information generation block suitable for generating error detection information for the state information;
a transmission management block suitable for generating the state information frame

Assignees

• Sk Hynix Inc

Inventors

• Lee Hak Dae

Classifications

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title