Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor

Patent metadata

Field	Value
Publication number	US-9507656-B2
Application number	US-42492909-A
Country	US
Kind code	B2
Filing date	Apr 16, 2009
Priority date	Apr 16, 2009
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

First claim

What is claimed is:

1. A processor, comprising:
a floating-point unit configured to execute an unfused multiply-accumulate instruction defined with an instruction set architecture, wherein the unfused multiply-accumulate instruction includes a multiply sub-operation and an accumulate sub-operation;
a storage configured to maintain floating-point exception state information; and
exception logic including a storage array and configured to capture uncommitted floating-point exception state within the storage array after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, and to update the storage, after the unfused multiply-accumulate instruction commits, with the floating-point exception state from the storage array;
wherein the storage array includes a first port and a second port; and
wherein the exception logic is further configured to:
read exception information for a first unfused multiply-accumulate instruction defined in the instruction set architecture from the first port in response to a determination that the first unfused multiply-accumulate instruction has committed;
read exception information for a second unfused multiply-accumulate instruction defined the in the instruction set architecture from the second port in response to a determination that the second unfused multiply-accumulate instruction has committed;
select one of the exception information for the first unfused multiply-accumulate instruction and the exception information for the second unfused multiply-accumulate instruction dependent upon which of the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction commits; and
determine an architectural state dependent upon the selected exception information;

wherein the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction are concurrently executed.

2. The processor as recited in claim 1 , wherein the floating-point unit is configured to provide one or more exception signals corresponding to one or more respective exceptions generated in response to execution of each of the multiply sub-operation and the accumulate sub-operation.

3. The processor as recited in claim 1 , wherein the floating-point exception state information includes accrued exception bits and current exception bits.

4. The processor as recited in claim 3 , wherein the floating-point unit is further configured to generate one or more particular accrued exception bits and one or more current exception bits that are indicative of the floating-point exception state after the multiply sub-operation and the accumulate sub-operation.

5. The processor as recited in claim 4 , wherein, to generate a given accrued exception bit, the exception logic is configured to perform a logical OR operation between a first exception signal generated after execution of the multiply sub-operation and a second exception signal generated after execution of the accumulate sub-operation.

6. The processor as recited in claim 3 , wherein the exception logic is further configured to discard floating-point exception bits corresponding to the floating-point exception state prior to updating the storage in response to one or more exception traps being enabled.

7. The processor as recited in claim 1 , wherein the floating-point unit is configured to execute a first instruction before a second instruction, wherein the second instruction occurs before the first instruction in program order.

8. The processor as recited in claim 1 , wherein the floating-point exceptions are defined in the IEEE Standard 754-1985.

9. The processor as recited in claim 1 , wherein during execution of an unfused multiply-accumulate instruction, the floating-point unit is further configured to perform a first rounding operation subsequent to the multiply sub-operation and a second rounding operation subsequent to the accumulate sub-operation.

10. A system comprising:
a system memory; and
a processor coupled to the system memory;
wherein the processor includes:
a floating-point unit configured to execute an unfused multiply-accumulate instruction defined with an instruction set architecture, wherein the unfused multiply-accumulate instruction includes a multiply sub-operation and an accumulate sub-operation;
a storage configured to maintain floating-point exception state information; and
exception logic including a storage array and configured to capture uncommitted floating-point exception state within the storage array after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, and to update the storage, after the unfused multiply-accumulate instruction commits, with the floating-point exception state from the storage array;
wherein the storage array includes a first port and a second port; and
wherein the exception logic is further configured to:
read exception information for a first unfused multiply-accumulate instruction defined in the instruction set architecture from the first port in response to a determination that the first unfused multiply-accumulate instruction has committed;
read exception information for a second unfused multiply-accumulate instruction defined in the instruction set architecture from the second port in response to a determination that the second unfused multiply-accumulate instruction has committed;
select one of the exception information for the first unfused multiply-accumulate instruction and the exception information for the second unfused multiply-accumulate instruction dependent upon which of the first unfused multiply-accumulate and the second unfused multiply-accumulate instruction commits; and
determine an architectural state dependent upon the selected exception information;

wherein the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction are concurrently executed.

11. A method comprising:
a floating-point unit of a processor executing an unfused multiply-accumulate instruction defined with an instruction set architecture, wherein the unfused multiply-accumulate instruction includes a multiply sub-operation and an accumulate sub-operation;
maintaining floating-point exception state information within a storage; and
exception logic capturing uncommitted floating-point exception state within a storage array of the exception logic after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, and updating the storage, after the unfused multiply-accumulate instruction commits, with the floating-point exception state from the storage array;
wherein the storage array includes a first port and a second port; and
wherein the exception logic is further configured to:
read exception information for a first unfused multiply-accumulate instruction defined in the instruction set architecture from the first port in response to a determination that the first unfused multiply-accumulate instruction has committed;
read exception information for a second unfused multiply-accumulate instruction defined in the instruction set architecture from the second port in response to a determination that the second unfused multiply-accumulate instruction as committed;
select one of the exception information for the first unfused multiply-accumulate instruction and the exception information for the second unfused multiply-accumulate instruction dependent upon which of the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction commits; and
determine an architectural state dependent upon the selected exception information;

Assignees

• Brooks Jeffrey S
• Jordan Paul J
• Olson Christopher H
• Oracle America Inc

Inventors

• Brooks Jeffrey S
• Jordan Paul J
• Olson Christopher H

Classifications

• G06F9/3853

  of compound instructions · CPC title

• G06F9/30014

  with variable precision · CPC title

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title