Multicore processor and method of use that configures core functions based on executing instructions

Patent metadata

Field	Value
Publication number	US-9507640-B2
Application number	US-33569608-A
Country	US
Kind code	B2
Filing date	Dec 16, 2008
Priority date	Dec 16, 2008
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.

First claim

What is claimed is:

1. A multiprocessor system comprising:
plural heterogeneous processing units;
a performance sensor associated with each processing unit and operable to determine one or more performance metrics for the associated processing unit;
a workload scheduler operable to simultaneously initiate a homogeneous instruction set on the plural heterogeneous processing units; and
a performance analyzer interfaced with the performance sensors, the performance analyzer operable to compare the performance metrics to select one of the plural heterogeneous processing units to execute the instruction set.

2. The multiprocessor system of claim 1 wherein each heterogeneous processing unit comprises plural cores, at least one processing unit having a proportionately greater number of integer cores relative to at least one other processing unit.

3. The multiprocessor system of claim 1 wherein each heterogeneous processing unit comprises plural cores, at least one processing unit having a proportionately greater number of floating point cores relative to at least one other processing unit.

4. The multiprocessor system of claim 1 wherein each heterogeneous processing unit comprises one or more prefetch engines, at least one processing unit having a proportionately greater number of prefetch engines relative to at least one other processing unit.

5. The multiprocessor system of claim 1 wherein the performance metric comprises cycles per instruction.

6. The multiprocessor system of claim 1 wherein the performance metric comprises cache miss rates.

7. The multiprocessor system of claim 1 wherein the performance metric comprises the number of prefetches.

8. The multiprocessor system of claim 1 wherein the workload scheduler is further operable to:
store performance metrics associated with the instruction set;
subsequently detect pending execution of the instruction set; and
schedule the instruction set for execution based on the stored performance metrics.

Assignees

• Capps Jr Louis B
• Newhart Ronald E
• Cook Thomas E
• Bell Jr Robert H
• Shapiro Michael J
• IBM

Inventors

• Capps Jr Louis B
• Newhart Ronald E
• Cook Thomas E
• Bell Jr Robert H
• Shapiro Michael J

Classifications

• G06F9/3802

  Instruction prefetching · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F2209/501

  Performance criteria · CPC title

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title