Processor loop buffer

Patent metadata

Field	Value
Publication number	US-9507600-B2
Application number	US-201414164633-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Jan 27, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method and apparatus for executing program loops. A processor, includes an execution unit and an instruction fetch buffer. The execution unit is configured to execute instructions. The instruction fetch buffer is configured to store instructions for execution by the execution unit. The instruction fetch buffer includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit. The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and to control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.

First claim

What is claimed is:

1. A processor, comprising:
an execution unit configured to execute instructions; and
an instruction fetch buffer configured to store instructions for execution by the execution unit, the instruction fetch buffer comprising:
a loop buffer configured to store instructions of an instruction loop for execution by the execution unit, the loop buffer comprising buffer control logic configured to:
predecode a loop jump instruction;
identify loop start and loop…

Assignees

• Texas Instruments Deutschland

Inventors

• Wiencke Christian
• Ledwa Ralph
• Reichel Norbert

Classifications

• G06F9/325 Primary

  Physics · mapped topic

• G06F9/381

  Physics · mapped topic

• G06F9/3013

  Physics · mapped topic

• G06F9/3814

  Physics · mapped topic