Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources

Patent metadata

Field	Value
Publication number	US-9507596-B2
Application number	US-201414471261-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Aug 28, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.

First claim

What is claimed is:

1. A processor, comprising:
a core;
a prefetcher, including circuitry to:
make speculative prefetch requests through a memory subsystem for an element for execution by the core; and
store prefetched elements in a cache; and

a prefetcher control module, including:
determine a first count of memory accesses to a first type of memory;
determine a second count of memory accesses to a second type of memory; and
based upon the first count, the second count, the first type, and the second type, reduce the speculative prefetch requests of the prefetcher.

2. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon a lower bandwidth of the second memory when compared to a bandwidth of the first memory.

3. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon:
a lower bandwidth of the second memory when compared to a bandwidth of the first memory; and
the second count exceeding a threshold value.

4. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon the second count exceeding a threshold value for a plurality of time periods.

5. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to:
reduce the speculative prefetch requests of the prefetcher further based upon the second count exceeding an upper threshold value; and
subsequent to reducing the speculative prefetch requests, increase the prefetch requests of the prefetcher based upon the second count subsequently falling below a lower threshold value, the lower threshold value different than the upper threshold value.

6. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon the first count being relatively less than the second count.

7. The processor of claim 1 , wherein the prefetcher control module further includes circuitry to increase the speculative prefetch requests of the prefetcher based upon the first count being relatively more than the second count.

8. A method comprising, within a processor:
making speculative prefetch requests through a memory subsystem for an element for execution by a core of the processor;
storing prefetched elements in a cache of the processor;
determining a first count of memory accesses to a first type of memory;
determining a second count of memory accesses to a second type of memory; and
reducing the speculative prefetch requests based upon the first type, the second type, the first count, and the second count.

9. The method of claim 8 , further comprising reducing the speculative prefetch requests based upon a lower bandwidth of the second memory when compared to a bandwidth of the first memory.

10. The method of claim 8 , further comprising reducing the speculative prefetch requests based upon:
a lower bandwidth of the second memory when compared to a bandwidth of the first memory; and
the second count exceeding a threshold value.

11. The method of claim 8 , further comprising reducing the speculative prefetch requests based upon the second count exceeding a threshold value for a plurality of time periods.

12. The method of claim 8 , further comprising:
reducing the speculative prefetch requests further based upon the second count exceeding an upper threshold value; and
subsequent to reducing the speculative prefetch requests, increasing the prefetch requests based upon the second count subsequently falling below a lower threshold value, the lower threshold value different than the upper threshold value.

13. The method of claim 8 , further comprising reducing the speculative prefetch requests based upon the first count being relatively less than the second count.

14. A system comprising:
a first memory of a first type;
a second memory of a second type; and
a processor, including:
a core;
a prefetcher, including circuitry to:
make speculative prefetch requests through a memory subsystem for an element for execution by the core; and
store prefetched elements in a cache; and

a prefetcher control module, including:
determine a first count of memory accesses to the first memory;
determine a second count of memory accesses to the second memory; and
based upon the first count and the second count, reduce the speculative prefetch requests of the prefetcher.

15. The system of claim 14 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon a lower bandwidth of the second memory when compared to a bandwidth of the first memory.

16. The system of claim 14 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon:
a lower bandwidth of the second memory when compared to a bandwidth of the first memory; and
the second count exceeding a threshold value.

17. The system of claim 14 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon the second count exceeding a threshold value for a plurality of time periods.

18. The system of claim 14 , wherein the prefetcher control module further includes circuitry to:
reduce the speculative prefetch requests of the prefetcher further based upon the second count exceeding an upper threshold value; and
subsequent to reducing the speculative prefetch requests, increase the prefetch requests of the prefetcher based upon the second count subsequently falling below a lower threshold value, the lower threshold value different than the upper threshold value.

19. The system of claim 14 , wherein the prefetcher control module further includes circuitry to reduce the speculative prefetch requests of the prefetcher further based upon the first count being relatively less than the second count.

20. The system of claim 14 , wherein the prefetcher control module further includes circuitry to increase the speculative prefetch requests of the prefetcher based upon the first count being relatively more than the second count.

Assignees

• Intel Corp

Inventors

• Jagannathan Ashok
• Jain Prabhat
• Vinod Krishna N
• Sodani Avinash

Classifications

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title