Flash memory controller and associated control method
US-2024377989-A1 · Nov 14, 2024 · US
US9507533B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507533-B2 |
| Application number | US-201514922596-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 26, 2015 |
| Priority date | May 21, 2013 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.
Opening claim text (preview).
We claim: 1. A storage controller system comprising: a host controller configured to: for a received host command, identify data being stored in a plurality of cache areas, each of the plurality of cache areas being associated with a different one of a plurality of storage areas, and the identified data comprising data that is to be sent to a host in response to receipt of the host command; determine that the identified data being stored in the plurality of cache areas and that…
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