Operation of software modules in parallel
US-2015324240-A1 · Nov 12, 2015 · US
Single core wakeup multi-core synchronization mechanism
US9507404B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507404-B2 |
| Application number | US-201414281621-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 19, 2014 |
| Priority date | Aug 28, 2013 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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Abstract
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A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.
First claim
Opening claim text (preview).
The invention claimed is: 1. A microprocessor, comprising: a plurality of cores; a cache memory shared by the cores; and a control unit, configured to individually put each of the cores to sleep by stopping a clock signal to the core; wherein each of the cores is configured to execute a sleep instruction and in response to make a respective request of the control unit to put the core to sleep; wherein the control unit is configured to: put each of the cores to sleep in re…
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- G06F1/3237Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F9/4418Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9507404B2 cover?
- A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request …
- Who is the assignee on this patent?
- Via Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F1/3237. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).