Current limit control with constant accuracy

Patent metadata

Field	Value
Publication number	US-9507357-B2
Application number	US-201414277276-A
Country	US
Kind code	B2
Filing date	May 14, 2014
Priority date	Nov 19, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

The present document relates to a current sensing and/or control circuit with reduced sensing errors. A current control circuit for controlling a load current into an electronic device is described. The current control circuit comprises an array of control transistors configured to adjust the load current provided at an output of the array of control transistors. The load current is drawn from a power supply at an input voltage. Furthermore, the power supply is coupled to an input of the array of control transistors. The circuit further comprises a reference transistor coupled to the power supply at an input of the reference transistor and a reference current source configured to draw a reference current at an output of the reference transistor.

First claim

What is claimed is:

1. A current control circuit for controlling a load current into an electronic device, the current control circuit comprising
an array of control transistors configured to adjust the load current provided at an output of the array of control transistors; wherein the load current is drawn from a power supply at an input voltage; wherein the power supply is coupled to an input of the array of control transistors;
a reference transistor coupled to the power supply at an input of the reference transistor;
a reference current source configured to draw a reference current at an output of the reference transistor;
a controller configured to select one or more control transistors from the array of control transistors; and
transistor control units configured to control the reference transistor to provide a reference on-resistance and to control the selected one or more control transistors to provide an array on-resistance; wherein the controller is configured to select the one or more control transistors such that a ratio of a target level of the load current and the reference current corresponds to a ratio of the reference on-resistance and the array on-resistance.

2. The current control circuit of claim 1 , the array of control transistors comprises a plurality of control transistors which are arranged in parallel.

3. The current control circuit of claim 1 , wherein
the control transistors from the array of control transistors exhibit control transistor dimensions;
the reference transistor exhibits reference transistor dimensions;
the controller is configured to select the one or more control transistors such that the ratio of the target level of the load current and the reference current corresponds to a ratio of the reference transistor dimensions and effective dimensions of the selected one or more control transistors; and
the effective dimensions are dependent on the control transistor dimensions of the selected one or more control transistors.

4. The current control circuit of claim 3 , wherein the control transistor dimensions and the reference transistor dimensions comprise length/widths ratios.

5. The current control circuit of claim 1 , wherein
the control transistors of the array of control transistors have substantially equal on-resistances; and
the controller is configured to select more or less control transistors to decrease or increase, respectively, the array on-resistance.

6. The current control circuit of claim 1 , wherein
the control transistors of the array of control transistors have different on-resistances;
the controller is configured to select different combinations of control transistors to adjust the array on-resistance.

7. The current control circuit of claim 6 , wherein
the array of control transistors comprises an ordered sequence of r control transistors;
the on-resistances of adjacent control transistors of the ordered sequence of control transistors differ by a factor ½ starting from a maximum on-resistance; and
the controller is configured to select one or more control transistors to provide array on-resistances in the range of the maximum on-resistance times [1, 1/(2 r −1)].

8. The current control circuit of claim 7 , wherein the reference on-resistance corresponds to the maximum on-resistance.

9. The current control circuit of claim 8 , wherein the electronic device is controlled in dependence of the comparison signal.

10. The current control circuit of claim 1 , further comprising a comparator unit configured to compare a reference voltage at the output of the reference transistor with a load voltage at the output of the array of control transistors, to yield a comparison signal; wherein the comparison signal is indicative of a level of the load current relative to the reference current.

11. The current control circuit of claim 1 , wherein the controller is configured to select different combinations of one or more control transistors to set different target levels of the load current.

12. The current control circuit of claim 1 , wherein the transistor control units are configured to maintain open the one or more control transistors from the array of control transistors, which have not been selected.

13. The current control circuit of claim 1 , wherein the controller is configured to select the one or more control transistors such that a relative deviation of the load current from the target level remains at or below a pre-determined threshold.

14. The current control circuit of claim 1 , wherein the array of control transistors and/or the reference transistor comprise metal oxide semiconductor transistors.

15. A method for controlling a load current into an electronic device, the method comprising
adjusting the load current provided at an output of an array of control transistors; wherein the load current is drawn from a power supply at an input voltage; wherein the power supply is coupled to an input of the array of control transistors;
providing a reference transistor coupled to the power supply at an input of the reference transistor;
drawing a reference current at an output of the reference transistor;
selecting one or more control transistors from the array of control transistors; and
controlling the reference transistor to provide a reference on-resistance and controlling the selected one or more control transistors to provide an array on-resistance; wherein the one or more control transistors are selected such that a ratio of a target level of the load current and the reference current corresponds to a ratio of the reference on-resistance and the array on-resistance.

16. The method of claim 15 , wherein said array of control transistors comprises a plurality of control transistors which are arranged in parallel.

17. The method of claim 15 , wherein
the control transistors from the array of control transistors exhibit control transistor dimensions;
the reference transistor exhibits reference transistor dimensions;
the controller is configured to select the one or more control transistors such that the ratio of the target level of the load current and the reference current corresponds to a ratio of the reference transistor dimensions and effective dimensions of the selected one or more control transistors; and

the effective dimensions are dependent on the control transistor dimensions of the selected one or more control transistors.

18. The method of claim 17 , wherein said control transistor dimensions and the reference transistor dimensions comprise length/widths ratios.

19. The method of claim 15 , wherein said current control circuit wherein
said control transistors of the array of control transistors have substantially equal on-resistances; and
said controller selects more or less control transistors to decrease or increase, respectively, the array on-resistance.

20. The method of claim 15 , wherein said current control circuit wherein
said control transistors of the array of control transistors have different on-resistances;
said controller selects different combinations of control transistors to adjust the array on-resistance.

21. The method of claim 20 , wherein said current control circuit wherein
the array of control transistors comprises an ordered sequence of r control transistors;
the on-resistances of adjacent control transistors of the ordered sequence of control transistors differ by a factor ½ starting from a maximum on-resistance; and
said controller selects one or more cont

Assignees

• Dialog Semiconductor Gmbh

Inventors

• Weis Marcus
• Drebinger Stephan
• Rigoni Fabio

Classifications

• G05F1/573 Primary

  with overcurrent detector · CPC title

• H02M2001/0009

  Electricity · mapped topic

• G05F1/46 Primary

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title