TMS/TDI and SIPO controller circuitry with tap and trace interfaces

Patent metadata

Field	Value
Publication number	US-9506985-B2
Application number	US-201615075808-A
Country	US
Kind code	B2
Filing date	Mar 21, 2016
Priority date	Feb 8, 1989
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

First claim

What is claimed is:

1. An integrated circuit, comprising:
(a) test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, a TDO output lead, a trace data output, a trace data input, and a trace control output;
(b) trace domain circuitry having trace control inputs, a trace clock input, and a trace data output; and
(c) controller circuitry having a TMS/TDI input lead, a clock input lead, and a TDO input lead, the controller circuitry being connected…

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G06F11/3466

  Physics · mapped topic

• G01R31/31723 Primary

  Physics · mapped topic

• G01R31/318572 Primary

  Physics · mapped topic

• G01R31/3177 Primary

  Physics · mapped topic

• G06F11/27

  Physics · mapped topic