Video decoder with multi-format vector processor and methods for use therewith

US9503741B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9503741-B2
Application numberUS-201113162265-A
CountryUS
Kind codeB2
Filing dateJun 16, 2011
Priority dateJun 8, 2011
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.

First claim

Opening claim text (preview).

What is claimed is: 1. A video decoder comprising: an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal; a video decoding device, coupled to the entropy decoding device, that includes: a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data; and a plurality of vector processor units, coupled to the memory module, for generating a decoded video signal from the EDC data based on a parallel processing of vector operations, wherein at least one of the plurality of vector processor units includes: a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates a dimensionality of the first input data and the second input data. 2. The video decoder of claim 1 wherein the first input data is formatted as a 1×8 matrix when the matrix input configuration data has a first value. 3. The video decoder of claim 2 wherein the first input data is formatted as an 8×8 matrix when the matrix input configuration data has a second value. 4. The video decoder of claim 1 wherein the second input data is formatted as a 1×8 matrix when the matrix input configuration data has a first value. 5. The video decoder of claim 4 wherein the second input data is formatted as an 8×8 matrix when the matrix input configuration data has a second value. 6. The video decoder of claim 1 wherein the first input data is formatted as a 4×4 matrix second input data is formatted as a 4×4 matrix when the matrix input configuration data has a first value. 7. The video decoder of claim 1 wherein the encoded video signal is encoded in accordance with a VP8 coding standard. 8. A method comprising: generating entropy decoded (EDC) data from an encoded video signal; and generating a decoded video signal from the EDC data, via a plurality of vector processor units that each operated based on a parallel processing of vector operations and in response to a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data, wherein at least one of the plurality of vector processor units operates by: generating output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates a dimensionality of the first input data and the second input data. 9. The method of claim 8 wherein the first input data is formatted as a 1×8 matrix when the matrix input configuration data has a first value. 10. The method of claim 9 wherein the first input data is formatted as an 8×8 matrix when the matrix input configuration data has a second value. 11. The method of claim 8 wherein the second input data is formatted as a 1×8 matrix when the matrix input configuration data has a first value. 12. The method of claim 11 wherein the second input data is formatted as an 8×8 matrix when the matrix input configuration data has a second value. 13. The method of claim 8 wherein the first input data is formatted as a 4×4 matrix second input data is formatted as a 4×4 matrix when the matrix input configuration data has a first value. 14. The method of claim 8 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

Assignees

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Classifications

  • using hierarchical techniques, e.g. scalability (H04N19/63 takes precedence) · CPC title

  • characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

  • Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264 · CPC title

  • Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title

  • H04N19/40Primary

    using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream · CPC title

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What does patent US9503741B2 cover?
A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a…
Who is the assignee on this patent?
Yang Kai, Liu Dong, Hong Edward, and 2 more
What technology area does this patent fall under?
Primary CPC classification H04N19/40. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).