Techniques associated with server transaction latency information

Patent metadata

Field	Value
Publication number	US-9503347-B2
Application number	US-201213976964-A
Country	US
Kind code	B2
Filing date	Dec 18, 2012
Priority date	Dec 18, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
circuitry for a network input/output device;
a time stamp module executed by the circuitry to place separate time stamps on ingress request packets destined for a server coupled to the network input/output device and place separate time stamps on egress response packets sourced from the server;
a capture module executed by the circuitry to capture portions of separate ingress request packets and portions of separate egress response packets, the captured portions to identify the separately time stamped ingress request packets and the separately time stamped egress response packets; and
a forward module executed by the circuitry to forward the captured portions with respective time stamps to circuitry maintained at the server using a transport protocol in compliance with a specification to include Management Component Transport Protocol (MCTP) Host Interface Specification, the circuitry maintained at the server included in a chipset;
the chipset a processor for the server, the processor to execute an operating system and a network input/output device driver implemented as part of the operating system, the forward module to forward the captured portion to the circuitry maintained at the server.

2. The apparatus of claim 1 , comprising the forwarded captured portions associated with one or more transactions, a given transaction to include a given ingress request packet that causes the server to generate a given egress response packet, the circuitry maintained at the server arranged to determine a transaction latency value based on the time stamps placed on the given ingress request and egress response packets.

3. The apparatus of claim 1 , comprising the capture module to capture portions with respective time stamps over a given time interval and the forward module arranged to forward the captured portions with respective time stamps at an end of the given time interval.

4. The apparatus of claim 1 , the captured portions with respective time stamps forwarded to the server comprises the captured portions forwarded to circuitry maintained at the server, the circuitry maintained at the server included in a chipset, the forward module to forward the captured portions to the circuitry maintained at the server.

5. The apparatus of claim 1 , comprising the ingress request and the egress response packets having transmission control protocol (TCP) and Internet protocol (IP) headers, the captured portions to include information from TCP and IP headers for the ingress request and egress response packets, the information to include a source IP address, a destination IP address, a source port or a destination port.

6. An apparatus, comprising:
circuitry for a server;
a request module executed by the circuitry to receive time stamped portions of ingress request packets and to place the received time stamped portions of the ingress request packets in a transaction table;
a response module executed by the circuitry to receive time stamped portions of egress response packets and to place the received time stamped portions of the egress response packets in the transaction table;
a match module executed by the circuitry to match time stamped portions of ingress request packets with time stamped portions of egress response packets placed in the transaction table based on information included with respective time stamped portions of the ingress request and the egress response packets, the time stamped portions of the ingress request packets and the egress response packets to include transmission control protocol (TCP) and Internet protocol (IP) header information, the TCP and IP header information to include a source IP address, a destination IP address, a source port or a destination port;
a latency module executed by the circuitry to use first and second time stamps for respective matched time stamped portions of ingress request and egress response packets to determine separate transaction latency values for transactions executed by the server; and
a power module executed by the circuitry to cause an amount of power provided to the server to be adjusted based on a comparison of transaction latency values determined by the latency module to a given transaction latency target value.

7. The apparatus of claim 6 , comprising:
a report module executed by the circuitry to report information associated with the determined separate transaction latency values to a management logic configured to manage a plurality of servers.

8. The apparatus of claim 7 , comprising:
a bucket module executed by the circuitry to gather the determined separate transaction latency values in a plurality of buckets, where each bucket associated with an incremented time difference and configured to maintain one or more of the separately determined transaction latency values based on a proximity of respective separately determined transaction latency values to a given incremented time difference, each incremented time difference based on a span of time between a lowest determined transaction latency value and a highest determined transaction latency value from among the determined separate transaction latency values gathered over a previous time interval; and
a sort module executed by the circuitry to determine which bucket from among the plurality of buckets includes an n th percentile determined transaction latency value, where n equals any positive integer less than or equal to 100, the sort module to sort the bucket including the n th percentile determined transaction latency value to determine a given transaction latency value that equals the n th percentile determined transaction latency value, the sort module to provide the given transaction latency value to the report module, the report module to include the given transaction latency value in the information reported to the management logic.

9. The apparatus of claim 8 , the n th percentile determined transaction latency value comprises n equal to 95 and the given transaction latency value has a value greater than or equal to 95% of separately determined transaction latency values gathered in the plurality of buckets over a current time interval.

10. The apparatus of claim 8 , comprising the plurality of buckets maintained in a memory for the server, the memory to include one of dynamic random access memory or static random access memory.

11. The apparatus of claim 6 , comprising the circuitry for the server maintained at a chipset for the server.

12. The apparatus of claim 7 , comprising the circuitry for the server included in a processor for the server arranged to execute an operating system for the server, the match module, the latency module and the report module included in a network input/output device driver implemented as part of the operating system.

13. The apparatus of claim 6 , comprising the latency module to erase matched time stamped portions of ingress request packets and erase matched time stamped portions of egress request packets from the transaction table following determination of the separate transaction latency values based on the matched time stamped portions of ingress request and egress response packets.

14. The apparatus of claim 6 , comprising the circuitry for the server maintained at a chipset for the server, the latency module included as part of a manageability engine at the chipset, the power module included as part of a power node manager at the chipset.

15. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed on a server cause the server to:
receive time

Assignees

• Intel Corp

Inventors

• Deval Manasi
• Daubert Jim
• Mann Eric
• Li Cong
• Rajappa Muralidhar Murali
• Chagam Reddy Anjaneya Reddy
• Wescott David
• Nagappan Ramkumar
• Kanjo Raed

Classifications

• H04L41/12

  Discovery or management of network topologies · CPC title

• H04L47/2425

  for supporting services specification, e.g. SLA · CPC title

• H04L1/1678

  where the control information is for timing, e.g. time stamps · CPC title

• H04L43/0894 Primary

  Packet rate · CPC title

• H04L67/1029 Primary

  using data related to the state of servers by a load balancer · CPC title