Method for low complexity decision metric compression of higher-order square-QAM constellation

Patent metadata

Field	Value
Publication number	US-9503305-B1
Application number	US-201514849281-A
Country	US
Kind code	B1
Filing date	Sep 9, 2015
Priority date	Sep 9, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

It is possible to compress log likelihood ratios (LLRs) by exploiting the mapping symmetry between bits in the same symbol. For example, two LLRs corresponding to the same dimension of a square Quadrature Amplitude Modulation (QAM) symbol can be compressed into a single compressed LLR that excludes the magnitude bits of one of the LLRs because the magnitude component of LLRs for bits corresponding to the same dimension of a square QAM symbol exhibit a piecewise linear relationship with one another. Similar techniques can be used to exploit piecewise linear relationships between a subset of constellation points in a non-square QAM constellation.

First claim

What is claimed:

1. A method for compressing soft output information, the method comprising:
receiving log likelihood ratios (LLRs) for a modulation symbol, the LLRs including at least a first LLR for a first binary information bit in the modulation symbol and a second LLR for a second binary information bit in the modulation symbol;
compressing the first LLR and the second LLR to obtain a compressed LLR, wherein a magnitude component of the second LLR is excluded from the compressed LLR; and
communicating the compressed LLR to a symbol de-interleaver.

2. The method of claim 1 , wherein the compressed LLR includes a first sign bit of the first LLR, a second sign bit of the second LLR, and a first set of magnitude bits of the first LLR.

3. The method of claim 2 , wherein a confidence level of the second sign bit of the second LLR is estimated by a downstream LLR de-compressor based on the first set of magnitude bits of the first LLR.

4. The method of claim 2 , wherein the first set of magnitude bits of the first LLR indicate a confidence level in the first sign bit of the first LLR, and wherein the compressed LLR does not include any bits indicating a confidence level in the second sign bit of the second LLR.

5. The method of claim 2 , wherein the compressed LLR consists of the first sign bit of the first LLR, the second sign bit of the second LLR, and the first set of magnitude bits of the first LLR.

6. The method of claim 2 , wherein the second LLR includes a second set of magnitude bits indicating a confidence level in the second sign bit of the second LLR, and the second set of magnitude bits being excluded from the compressed LLR.

7. The method of claim 6 , wherein the second set of magnitude bits of the second LLR are estimated by a downstream LLR de-compressor based on the first sign bit of the first LLR, the second sign bit of the second LLR, and the first set of magnitude bits of the first LLR.

8. The method of claim 6 , wherein the second set of magnitude bits are estimated in accordance with a statistical correlation between confidence levels of the first binary information bit and the second binary information bit.

9. The method of claim 1 , wherein both the first binary information bit and the second binary information bit correspond to the same dimension of the modulation symbol.

10. The method of claim 1 , wherein the modulation symbol is a square quadrature amplitude modulation (QAM) symbol.

11. The method of claim 1 , wherein the modulation symbol is a Quadrature Phase Shift Keying (QPSK) symbol.

12. An apparatus comprising:
a processor; and
a computer readable storage medium storing programming instructions executed by the processor to:
receive log likelihood ratios (LLRs) for a modulation symbol, the LLRs including
at least a first LLR for a first binary information bit in the modulation symbol and a second LLR for a second binary information bit in the modulation symbol;
compress the first LLR and the second LLR to obtain a compressed LLR, wherein
a magnitude component of the second LLR is excluded from the compressed LLR; and
communicate the compressed LLR to a symbol de-interleaver.

13. The apparatus of claim 12 , wherein the compressed LLR includes a first sign bit of the first LLR, a second sign bit of the second LLR, and a first set of magnitude bits of the first LLR.

14. The apparatus of claim 13 , wherein the compressed LLR consists of the first sign bit of the first LLR, the second sign bit of the second LLR, and the first set of magnitude bits of the first LLR.

15. The apparatus of claim 14 , wherein the second LLR includes a second set of magnitude bits indicating a confidence level in the second sign bit, and the second set of magnitude bits being excluded from the compressed LLR.

16. A method for de-compressing soft output information, the method comprising:
receiving a compressed log likelihood ratio (LLR), the compressed LLR including a first sign bit indicating a value of a first binary information bit in a modulation symbol, a first set of magnitude bits indicating a confidence level of the first sign bit, and a second sign bit indicating a value of a second binary information bit in the modulation symbol;
decompressing the compressed LLR to obtain a first LLR for the first binary information bit and a second LLR for the second binary information bit, the first LLR comprising the first sign bit and the first set of magnitude bits, and the second LLR comprising the second sign bit and a second set of magnitude bits indicating a confidence level in the second sign bit, wherein the second set of magnitude bits are excluded from the compressed LLR; and
communicating the first LLR and the second LLR to a bit-level decoder.

17. The method of claim 16 , wherein the compressed LLR consists of the first sign bit, the second sign bit, and the first set of magnitude bits.

18. The method of claim 16 , wherein decompressing the compressed LLR comprises estimating the confidence level of the second sign bit based on a correlation between confidence levels of the first binary information bit and the second binary information bit.

19. The method of claim 16 , wherein both the first binary information bit and the second binary information bit correspond to the same dimension of the modulation symbol.

20. An apparatus comprising:
a processor; and
a computer readable storage medium storing programming instructions executed by the processor to:
receive a compressed log likelihood ratio (LLR), the compressed LLR including a first sign bit indicating a value of a first binary information bit in a modulation symbol, a first set of magnitude bits indicating a confidence level of the first sign bit, and a second sign bit indicating a value of a second binary information bit in the modulation symbol;
decompress the compressed LLR to obtain a first LLR for the first binary information bit and a second LLR for the second binary information bit, the first LLR comprising the first sign bit and the first set of magnitude bits, and the second LLR comprising the second sign bit and a second set of magnitude bits indicating a confidence level in the second sign bit; and
communicate the first LLR and the second LLR to a bit-level decoder, wherein the second set of magnitude bits are excluded from the compressed LLR.

21. The apparatus of claim 20 , wherein the compressed LLR consists of the first sign bit, the second sign bit, and the first set of magnitude bits.

22. The apparatus of claim 20 , wherein when decompressing the compressed LLR, the processor estimates the confidence level of the second sign bit based on a correlation between confidence levels of the first binary information bit and the second binary information bit.

23. The apparatus of claim 12 , wherein both the first binary information bit and the second binary information bit correspond to the same dimension of the modulation symbol.

24. The apparatus of claim 20 , wherein both the first binary information bit and the second binary information bit correspond to the same dimension of the modulation symbol.

Assignees

• Huawei Tech Co Ltd

Inventors

• Mitra Jeebak
• Zhang Zhuhong

Classifications

• H04L1/0003

  by switching between different modulation schemes · CPC title

• H04L27/36 Primary

  Modulator circuits; Transmitter circuits · CPC title

• H04L1/004

  by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00) · CPC title

• H04L27/34

  Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems · CPC title

• H04L1/0047 Primary

  Decoding adapted to other signal detection operation (in conjunction with sequence estimation or equalization H04L25/03286) · CPC title