Phase frequency detector (pfd) circuit with improved lock time
US-2016112055-A1 · Apr 21, 2016 · US
Phase frequency detector (PFD) circuit with improved lock time
US9503105B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9503105-B2 |
| Application number | US-201514868785-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2015 |
| Priority date | Oct 20, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
First claim
Opening claim text (preview).
What is claimed is: 1. A locking circuit to provide a clock output signal according to a reference clock signal, comprising: a controlled oscillator including an output to provide an oscillator output clock signal according to a control voltage signal; a feedback circuit including a first output to provide a feedback clock signal according to the oscillator output clock signal; a loop filter circuit comprising an impedance and a second output to provide the control voltage sig…
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- H03L7/095Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9503105B2 cover?
- Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a se…
- Who is the assignee on this patent?
- Texas Instruments Inc
- What technology area does this patent fall under?
- Primary CPC classification H03L7/095. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).